36 US patents granted on 22 July 2008 and assigned to Intel
| 1 | 7,404,193 | Method, system, and program for accessing device driver functions |
| 2 | 7,404,099 | Phase-locked loop having dynamically adjustable up/down pulse widths |
| 3 | 7,404,067 | Method and apparatus for efficient utilization for prescient instruction prefetch |
| 4 | 7,404,065 | Flow optimization and prediction for VSSE memory operations |
| 5 | 7,404,055 | Memory transfer with early access to critical portion |
| 6 | 7,404,047 | Method and apparatus to improve multi-CPU system performance for accesses to memory |
| 7 | 7,404,043 | Cache memory to support a processor’s power mode of operation |
| 8 | 7,404,040 | Packet data placement in a processor cache |
| 9 | 7,404,016 | Enhanced power reduction capabilities for streaming direct memory access engine |
| 10 | 7,403,925 | Entitlement security and control |
| 11 | 7,403,679 | Thermally tunable optical dispersion compensation devices |
| 12 | 7,403,584 | Programmable phase interpolator adjustment for ideal data eye sampling |
| 13 | 7,403,521 | Multicast and broadcast operations in ethernet switches |
| 14 | 7,403,512 | Service discovery architecture and method for wireless networks |
| 15 | 7,403,497 | Data transport between a media gateway and server |
| 16 | 7,403,426 | Memory with dynamically adjustable supply |
| 17 | 7,403,222 | Determining a final exposure setting automatically for a sold state camera without a separate light metering circuit |
| 18 | 7,403,172 | Reconfigurable patch antenna apparatus, systems, and methods |
| 19 | 7,403,053 | Power supply dependent delay compensation |
| 20 | 7,403,034 | PVT controller for programmable on die termination |
| 21 | 7,403,027 | Apparatuses and methods for outputting signals during self-heat burn-in modes of operation |
| 22 | 7,402,985 | Dual path linear voltage regulator |
| 23 | 7,402,958 | Display power partitioning |
| 24 | 7,402,909 | Microelectronic package interconnect and method of fabrication thereof |
| 25 | 7,402,875 | Lateral undercut of metal gate in SOI device |
| 26 | 7,402,872 | Method for forming an integrated circuit |
| 27 | 7,402,856 | Non-planar microelectronic device having isolation element to mitigate fringe effects and method to fabricate same |
| 28 | 7,402,519 | Interconnects having sealing structures to enable selective metal capping layers |
| 29 | 7,402,515 | Method of forming through-silicon vias with stress buffer collars and resulting devices |
| 30 | 7,402,509 | Method of forming self-passivating interconnects and resulting devices |
| 31 | 7,402,501 | Method of manufacturing a coaxial trace in a surrounding material, coaxial trace formed thereby, and semiconducting material containing same |
| 32 | 7,402,229 | Fabrication and use of semipermeable membranes and gels for the control of electrolysis in a microfluidic device |
| 33 | 7,402,182 | High-power LGA socket |
| 34 | 7,402,048 | Technique for blind-mating daughtercard to mainboard |
| 35 | 7,401,986 | Method and apparatus to generate and monitor optical signals and control power levels thereof in a planar lightwave circuit |
| 36 | 7,401,737 | Apparatus and method for a mobile personal computer system (MPC) with a built-in scanner |
