33 US patents granted on 22 July 2008 and assigned to Micron
| 1 | 7,404,162 | Buffering technique using structured delay skewing |
| 2 | 7,404,124 | On-chip sampling circuit and method |
| 3 | 7,404,071 | Memory modules having accurate operating current values stored thereon and methods for fabricating and implementing such devices |
| 4 | 7,404,066 | Active memory command engine and method |
| 5 | 7,404,033 | Method for reading while writing to a single partition flash memory |
| 6 | 7,403,444 | Selectable memory word line deactivation |
| 7 | 7,403,425 | Programming a flash memory device |
| 8 | 7,403,423 | Sensing scheme for low-voltage flash memory |
| 9 | 7,403,419 | Integrated DRAM-NVRAM multi-level memory |
| 10 | 7,403,416 | Integrated DRAM-NVRAM multi-level memory |
| 11 | 7,403,060 | Forward biasing protection circuit |
| 12 | 7,403,044 | Method of producing balanced data output |
| 13 | 7,403,033 | MOS linear region impedance curvature correction |
| 14 | 7,402,908 | Intermediate semiconductor device structures |
| 15 | 7,402,902 | Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice |
| 16 | 7,402,879 | Layered magnetic structures having improved surface planarity for bit material deposition |
| 17 | 7,402,876 | Zr– Sn–Ti–O films |
| 18 | 7,402,861 | Memory cells and select gates of NAND memory arrays |
| 19 | 7,402,850 | Back-side trapped non-volatile memory device |
| 20 | 7,402,833 | Multilayer dielectric tunnel barrier used in magnetic tunnel junction devices, and its method of fabrication |
| 21 | 7,402,789 | Methods for pixel binning in an image sensor |
| 22 | 7,402,533 | Masking without photolithography during the formation of a semiconductor device |
| 23 | 7,402,526 | Plasma processing, deposition, and ALD methods |
| 24 | 7,402,518 | Atomic layer deposition methods |
| 25 | 7,402,516 | Method for making integrated circuits |
| 26 | 7,402,512 | High aspect ratio contact structure with reduced silicon consumption |
| 27 | 7,402,498 | Methods of forming trench isolation regions |
| 28 | 7,402,489 | Capacitor compatible with high dielectric constant materials having a low contact resistance layer and the method for forming same |
| 29 | 7,402,453 | Microelectronic imaging units and methods of manufacturing microelectronic imaging units |
| 30 | 7,402,451 | Optimized transistor for imager device |
| 31 | 7,402,379 | Resist exposure system and method of forming a pattern on a resist |
| 32 | 7,402,259 | Chemical-mechanical polishing methods |
| 33 | 7,402,094 | Fixed-abrasive chemical-mechanical planarization of titanium nitride |
