39 US patents granted on 12 August 2008 and assigned to Intel
| 1 | 7,412,627 | Method and apparatus for providing debug functionality in a buffered memory channel |
| 2 | 7,412,619 | Integrated circuit capable of error management |
| 3 | 7,412,595 | Customization of electronic devices via pre-boot space |
| 4 | 7,412,584 | Data alignment micro-architecture systems and methods |
| 5 | 7,412,569 | System and method to track changes in memory |
| 6 | 7,412,568 | Method for thread caching |
| 7 | 7,412,565 | Memory optimization for a computer system having a hibernation mode |
| 8 | 7,412,562 | Using non-volatile memories for disk caching of partition table entries |
| 9 | 7,412,551 | Methods and apparatus for supporting programmable burst management schemes on pipelined buses |
| 10 | 7,412,540 | Data encoding and decoding in a data storage system |
| 11 | 7,412,536 | Method and system for a network node for attachment to switch fabrics |
| 12 | 7,412,520 | Systems and methods for recoverable workflow |
| 13 | 7,412,471 | Discrete filter having a tap selection circuit |
| 14 | 7,412,353 | Reliable computing with a many-core processor |
| 15 | 7,412,346 | Real-time temperture detection during test |
| 16 | 7,412,342 | Low cost test for IC’s or electrical modules using standard reconfigurable logic devices |
| 17 | 7,412,221 | Crosstalk reduction method, apparatus, and system |
| 18 | 7,412,123 | Hybrid free space fiber backplane |
| 19 | 7,412,057 | Fast-software-implemented pseudo-random code generator |
| 20 | 7,411,995 | Apparatus and related methods to aid in system identification in a heterogeneous communication system environment |
| 21 | 7,411,969 | Method, system, and apparatus for a credit based flow control in a computer system |
| 22 | 7,411,968 | Two-dimensional queuing/de-queuing methods and systems for implementing the same |
| 23 | 7,411,936 | Wireless communication method and apparatus |
| 24 | 7,411,902 | Method and system for maintaining partial order of packets |
| 25 | 7,411,821 | Method and apparatus to protect nonvolatile memory from viruses |
| 26 | 7,411,631 | Power management for processor-based appliances |
| 27 | 7,411,591 | Graphics memory switch |
| 28 | 7,411,533 | ADC for simultaneous multiple analog inputs |
| 29 | 7,411,505 | Switch status and RFID tag |
| 30 | 7,411,470 | Controlling coupling strength in electromagnetic bus coupling |
| 31 | 7,411,469 | Circuit arrangement |
| 32 | 7,411,337 | Electrical energy-generating system and devices and methods related thereto |
| 33 | 7,411,296 | Method, system, and apparatus for gravity assisted chip attachment |
| 34 | 7,411,269 | Isolation structure configurations for modifying stresses in semiconductor devices |
| 35 | 7,411,268 | Fabricating deeper and shallower trenches in semiconductor structures |
| 36 | 7,410,884 | 3D integrated circuits using thick metal for backside connections and offset bumps |
| 37 | 7,410,858 | Isolation structure configurations for modifying stresses in semiconductor devices |
| 38 | 7,410,763 | Multiplex data collection and analysis in bioanalyte detection |
| 39 | 7,410,733 | Dual-layer EUV mask absorber with trenches having opposing sidewalls that are straight and parallel |
