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	<title>Latest Patents &#187; Intel</title>
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		<title>Intel patent applications published on 02 September 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-02-september-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-02-september-2010/#comments</comments>
		<pubDate>Thu, 02 Sep 2010 13:47:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10360</guid>
		<description><![CDATA[No US patent applications published on 02 September 2010 and assigned to Intel
]]></description>
			<content:encoded><![CDATA[<p>No US patent applications published on 02 September 2010 and assigned to Intel</p>
]]></content:encoded>
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		<title>Intel patents granted on 31 August 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-31-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-31-august-2010/#comments</comments>
		<pubDate>Tue, 31 Aug 2010 16:10:28 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10318</guid>
		<description><![CDATA[36 US patents granted on 31 August 2010 and assigned to Intel



1
7,788,713
Method, apparatus and system for virtualized peer-to-peer proxy services


2
7,788,670
Performance-based workload scheduling in multi-core architectures


3
7,788,653
Apparatus and methods for performing generational escape analysis in managed runtime environments


4
7,788,650
Compiler-based critical section amendment for a multiprocessor environment


5
7,788,519
Method, system, and apparatus for improving multi-core processor performance


6
7,788,494
Link key injection mechanism for [...]]]></description>
			<content:encoded><![CDATA[<p>36 US patents granted on 31 August 2010 and assigned to Intel<br />
<span id="more-10318"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,713" target="_blank" rel="nofollow">7,788,713</a></td>
<td valign="top">Method, apparatus and system for virtualized peer-to-peer proxy services</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,670" target="_blank" rel="nofollow">7,788,670</a></td>
<td valign="top">Performance-based workload scheduling in multi-core architectures</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,653" target="_blank" rel="nofollow">7,788,653</a></td>
<td valign="top">Apparatus and methods for performing generational escape analysis in managed runtime environments</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,650" target="_blank" rel="nofollow">7,788,650</a></td>
<td valign="top">Compiler-based critical section amendment for a multiprocessor environment</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,519" target="_blank" rel="nofollow">7,788,519</a></td>
<td valign="top">Method, system, and apparatus for improving multi-core processor performance</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,494" target="_blank" rel="nofollow">7,788,494</a></td>
<td valign="top">Link key injection mechanism for personal area networks</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,475" target="_blank" rel="nofollow">7,788,475</a></td>
<td valign="top">Booting utilizing electronic mail</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,460" target="_blank" rel="nofollow">7,788,460</a></td>
<td valign="top">Defragmenting objects in a storage medium</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,392" target="_blank" rel="nofollow">7,788,392</a></td>
<td valign="top">Mechanism for universal media redirection control</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,391" target="_blank" rel="nofollow">7,788,391</a></td>
<td valign="top">Using a threshold value to control mid-interrupt polling</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,917" target="_blank" rel="nofollow">7,787,917</a></td>
<td valign="top">Folding electronic device with continuous display</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,891" target="_blank" rel="nofollow">7,787,891</a></td>
<td valign="top">Mobile station localization apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,836" target="_blank" rel="nofollow">7,787,836</a></td>
<td valign="top">Multiple radios communication device and a method thereof</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,698" target="_blank" rel="nofollow">7,787,698</a></td>
<td valign="top">Sign coding and decoding</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,660" target="_blank" rel="nofollow">7,787,660</a></td>
<td valign="top">Fingerprint detecting wireless device</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,651" target="_blank" rel="nofollow">7,787,651</a></td>
<td valign="top">Triangular method for hypotheses filtration in a cognitive control framework</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,627" target="_blank" rel="nofollow">7,787,627</a></td>
<td valign="top">Methods and apparatus for providing a key management system for wireless communication networks</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,567" target="_blank" rel="nofollow">7,787,567</a></td>
<td valign="top">Beamforming by antenna puncturing</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,487" target="_blank" rel="nofollow">7,787,487</a></td>
<td valign="top">Systems and methods for contention control in wireless networks</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,470" target="_blank" rel="nofollow">7,787,470</a></td>
<td valign="top">Dynamic quality of service (QOS) provisioning using session initiation protocol (SIP) module in wireless base stations</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,418" target="_blank" rel="nofollow">7,787,418</a></td>
<td valign="top">Apparatus and method to support VoIP calls for mobile subscriber stations</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,410" target="_blank" rel="nofollow">7,787,410</a></td>
<td valign="top">Communication within a wireless network using multiple signal transmission powers</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,406" target="_blank" rel="nofollow">7,787,406</a></td>
<td valign="top">Methods and arrangements for adaptively changing snoozing intervals of wireless devices</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,403" target="_blank" rel="nofollow">7,787,403</a></td>
<td valign="top">Apparatus and method for adjusting a duty cycle to save power in a computing system</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,398" target="_blank" rel="nofollow">7,787,398</a></td>
<td valign="top">Minimizing mutual interference for multi-radio co-existence platforms</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,352" target="_blank" rel="nofollow">7,787,352</a></td>
<td valign="top">Method for processing a MEMS/CMOS cantilever based memory storage device</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,292" target="_blank" rel="nofollow">7,787,292</a></td>
<td valign="top">Carbon nanotube fuse element</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,291" target="_blank" rel="nofollow">7,787,291</a></td>
<td valign="top">Programming a multilevel phase change memory cell</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,991" target="_blank" rel="nofollow">7,786,991</a></td>
<td valign="top">Applications of interval arithmetic for reduction of number of computations in ray tracing problems</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,914" target="_blank" rel="nofollow">7,786,914</a></td>
<td valign="top">Time-interleaved delta-sigma modulator</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,769" target="_blank" rel="nofollow">7,786,769</a></td>
<td valign="top">On die signal detector without die power</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,722" target="_blank" rel="nofollow">7,786,722</a></td>
<td valign="top">Automated tray transfer device for prevention of mixing post and pre-test dies, and method of using same</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,654" target="_blank" rel="nofollow">7,786,654</a></td>
<td valign="top">Compact rake piezoelectric assembly and method of manufacturing same</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,958" target="_blank" rel="nofollow">7,785,958</a></td>
<td valign="top">Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,114" target="_blank" rel="nofollow">7,785,114</a></td>
<td valign="top">Modification of connections between a die package and a system board</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,784,178" target="_blank" rel="nofollow">7,784,178</a></td>
<td valign="top">Higher performance barrier materials for containers of environmentally sensitive semiconductor fabrication devices</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 26 August 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-26-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-26-august-2010/#comments</comments>
		<pubDate>Thu, 26 Aug 2010 14:34:14 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10276</guid>
		<description><![CDATA[1 US patent application published on 26 August 2010 and assigned to Intel



1
20100213581
DIELECTRIC FILM WITH LOW COEFFICIENT OF THERMAL EXPANSION (CTE) USING LIQUID CRYSTALLINE RESIN


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 26 August 2010 and assigned to Intel<br />
<span id="more-10276"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100213581.PGNR.&#038;OS=DN/20100213581RS=DN/20100213581" target="_blank">20100213581</a></td>
<td valign="top">DIELECTRIC FILM WITH LOW COEFFICIENT OF THERMAL EXPANSION (CTE) USING LIQUID CRYSTALLINE RESIN</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 24 August 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-24-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-24-august-2010/#comments</comments>
		<pubDate>Tue, 24 Aug 2010 13:15:59 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10236</guid>
		<description><![CDATA[29 US patents granted on 24 August 2010 and assigned to Intel



1
7,784,095
Virtual private network using dynamic physical adapter emulation


2
7,784,094
Stateful packet content matching mechanisms


3
7,784,060
Efficient virtual machine communication via virtual machine queues


4
7,784,057
Single-stack model for high performance parallelism


5
7,783,959
Apparatus and method for reduced power consumption communications over a physical interconnect


6
7,783,871
Method to remove stale branch predictions for an instruction prior [...]]]></description>
			<content:encoded><![CDATA[<p>29 US patents granted on 24 August 2010 and assigned to Intel<br />
<span id="more-10236"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,784,095" target="_blank" rel="nofollow">7,784,095</a></td>
<td valign="top">Virtual private network using dynamic physical adapter emulation</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,784,094" target="_blank" rel="nofollow">7,784,094</a></td>
<td valign="top">Stateful packet content matching mechanisms</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,784,060" target="_blank" rel="nofollow">7,784,060</a></td>
<td valign="top">Efficient virtual machine communication via virtual machine queues</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,784,057" target="_blank" rel="nofollow">7,784,057</a></td>
<td valign="top">Single-stack model for high performance parallelism</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,959" target="_blank" rel="nofollow">7,783,959</a></td>
<td valign="top">Apparatus and method for reduced power consumption communications over a physical interconnect</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,871" target="_blank" rel="nofollow">7,783,871</a></td>
<td valign="top">Method to remove stale branch predictions for an instruction prior to execution within a microprocessor</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,819" target="_blank" rel="nofollow">7,783,819</a></td>
<td valign="top">Integrating non-peripheral component interconnect (PCI) resources into a personal computer system</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,809" target="_blank" rel="nofollow">7,783,809</a></td>
<td valign="top">Virtualization of pin functionality in a point-to-point interface</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,769" target="_blank" rel="nofollow">7,783,769</a></td>
<td valign="top">Accelerated TCP (Transport Control Protocol) stack processing</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,497" target="_blank" rel="nofollow">7,783,497</a></td>
<td valign="top">Method of adaptive browsing for digital content</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,114" target="_blank" rel="nofollow">7,783,114</a></td>
<td valign="top">Training and using classification components on multiple processing units</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,970" target="_blank" rel="nofollow">7,782,970</a></td>
<td valign="top">Apparatus and associated methods to introduce diversity in a multicarrier communication channel</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,939" target="_blank" rel="nofollow">7,782,939</a></td>
<td valign="top">Real time bit rate control system</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,921" target="_blank" rel="nofollow">7,782,921</a></td>
<td valign="top">Integrated optical detector in semiconductor reflector</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,905" target="_blank" rel="nofollow">7,782,905</a></td>
<td valign="top">Apparatus and method for stateless CRC calculation</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,887" target="_blank" rel="nofollow">7,782,887</a></td>
<td valign="top">Method and apparatus for driving data packets</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,829" target="_blank" rel="nofollow">7,782,829</a></td>
<td valign="top">Energy-efficient link adaptation and resource allocation for wireless OFDMA systems</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,825" target="_blank" rel="nofollow">7,782,825</a></td>
<td valign="top">Methods and arrangements for link rate adaptation in multi-radio co-existence platforms</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,817" target="_blank" rel="nofollow">7,782,817</a></td>
<td valign="top">Systems and techniques for improved data throughput in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,754" target="_blank" rel="nofollow">7,782,754</a></td>
<td valign="top">Method and apparatus to support SDMA transmission of a OFDMA based network</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,649" target="_blank" rel="nofollow">7,782,649</a></td>
<td valign="top">Using controlled bias voltage for data retention enhancement in a ferroelectric media</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,304" target="_blank" rel="nofollow">7,782,304</a></td>
<td valign="top">System and apparatus for adjustable keyboard arrangements</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,104" target="_blank" rel="nofollow">7,782,104</a></td>
<td valign="top">Delay element array for time-to-digital converters</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,889" target="_blank" rel="nofollow">7,781,889</a></td>
<td valign="top">Shielded via</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,771" target="_blank" rel="nofollow">7,781,771</a></td>
<td valign="top">Bulk non-planar transistor having strained enhanced mobility and methods of fabrication</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,682" target="_blank" rel="nofollow">7,781,682</a></td>
<td valign="top">Methods of fabricating multichip packages and structures formed thereby</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,260" target="_blank" rel="nofollow">7,781,260</a></td>
<td valign="top">Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,780,360" target="_blank" rel="nofollow">7,780,360</a></td>
<td valign="top">Method and apparatus to generate and monitor optical signals and control power levels thereof in a planar lightwave circuit</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,638" target="_blank" rel="nofollow">7,779,638</a></td>
<td valign="top">Localized microelectronic cooling apparatuses and associated methods and systems</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patent applications published on 19 August 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-19-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-19-august-2010/#comments</comments>
		<pubDate>Thu, 19 Aug 2010 14:33:58 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10196</guid>
		<description><![CDATA[2 US patent applications published on 19 August 2010 and assigned to Intel



1
20100210072
Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer


2
20100208579
ADAPTIVE USE OF A TRANSMIT OPPORTUNITY


]]></description>
			<content:encoded><![CDATA[<p>2 US patent applications published on 19 August 2010 and assigned to Intel<br />
<span id="more-10196"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100210072.PGNR.&#038;OS=DN/20100210072RS=DN/20100210072" target="_blank">20100210072</a></td>
<td valign="top">Buffer coating having a physical mixture of high toughness polymer and a low shrinkage polymer</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100208579.PGNR.&#038;OS=DN/20100208579RS=DN/20100208579" target="_blank">20100208579</a></td>
<td valign="top">ADAPTIVE USE OF A TRANSMIT OPPORTUNITY</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Intel patents granted on 17 August 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-17-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-17-august-2010/#comments</comments>
		<pubDate>Tue, 17 Aug 2010 13:59:53 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10157</guid>
		<description><![CDATA[30 US patents granted on 17 August 2010 and assigned to Intel



1
7,779,451
Securing wakeup network events


2
7,779,305
Method and system for recovery from an error in a computing device by transferring control from a virtual machine monitor to separate firmware instructions


3
7,779,294
Power-safe disk storage apparatus, systems, and methods


4
7,779,287
Reducing power consumption in multiprocessor systems


5
7,779,282
Maintaining network connectivity while operating in low [...]]]></description>
			<content:encoded><![CDATA[<p>30 US patents granted on 17 August 2010 and assigned to Intel<br />
<span id="more-10157"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,451" target="_blank" rel="nofollow">7,779,451</a></td>
<td valign="top">Securing wakeup network events</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,305" target="_blank" rel="nofollow">7,779,305</a></td>
<td valign="top">Method and system for recovery from an error in a computing device by transferring control from a virtual machine monitor to separate firmware instructions</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,294" target="_blank" rel="nofollow">7,779,294</a></td>
<td valign="top">Power-safe disk storage apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,287" target="_blank" rel="nofollow">7,779,287</a></td>
<td valign="top">Reducing power consumption in multiprocessor systems</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,282" target="_blank" rel="nofollow">7,779,282</a></td>
<td valign="top">Maintaining network connectivity while operating in low power mode</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,244" target="_blank" rel="nofollow">7,779,244</a></td>
<td valign="top">Multi-socket boot</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,243" target="_blank" rel="nofollow">7,779,243</a></td>
<td valign="top">Dual operating system computing system</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,239" target="_blank" rel="nofollow">7,779,239</a></td>
<td valign="top">User opt-in processor feature control capability</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,211" target="_blank" rel="nofollow">7,779,211</a></td>
<td valign="top">Reducing latency in responding to a snoop request</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,210" target="_blank" rel="nofollow">7,779,210</a></td>
<td valign="top">Avoiding snoop response dependency</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,193" target="_blank" rel="nofollow">7,779,193</a></td>
<td valign="top">Method and apparatus for external data transfer in a personal storage device</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,188" target="_blank" rel="nofollow">7,779,188</a></td>
<td valign="top">System and method to reduce memory latency in microprocessor systems connected with a bus</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,178" target="_blank" rel="nofollow">7,779,178</a></td>
<td valign="top">Method and apparatus for application/OS triggered low-latency network communications</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,838" target="_blank" rel="nofollow">7,778,838</a></td>
<td valign="top">Apparatus, system and method for buffering audio data to allow low power states in a processing system during audio playback</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,826" target="_blank" rel="nofollow">7,778,826</a></td>
<td valign="top">Beamforming codebook generation system and associated methods</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,817" target="_blank" rel="nofollow">7,778,817</a></td>
<td valign="top">Method and apparatus for determining text passage similarity</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,657" target="_blank" rel="nofollow">7,778,657</a></td>
<td valign="top">Method and apparatus to perform power control in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,599" target="_blank" rel="nofollow">7,778,599</a></td>
<td valign="top">Aggregated channel feedback</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,334" target="_blank" rel="nofollow">7,778,334</a></td>
<td valign="top">Modulation scheme for communication environments</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,226" target="_blank" rel="nofollow">7,778,226</a></td>
<td valign="top">Device, system and method of coordination among multiple transceivers</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,166" target="_blank" rel="nofollow">7,778,166</a></td>
<td valign="top">Synchronizing sequence numbers among peers in a network</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,777,544" target="_blank" rel="nofollow">7,777,544</a></td>
<td valign="top">System and method to detect order and linearity of signals</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,777,507" target="_blank" rel="nofollow">7,777,507</a></td>
<td valign="top">Integrated circuit testing with laser stimulation and emission analysis</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,777,282" target="_blank" rel="nofollow">7,777,282</a></td>
<td valign="top">Self-aligned tunneling pocket in field-effect transistors and processes to form same</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,734" target="_blank" rel="nofollow">7,776,734</a></td>
<td valign="top">Barrier layer for fine-pitch mask-based substrate bumping</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,729" target="_blank" rel="nofollow">7,776,729</a></td>
<td valign="top">Transistor, method of manufacturing same, etchant for use during manufacture of same, and system containing same</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,684" target="_blank" rel="nofollow">7,776,684</a></td>
<td valign="top">Increasing the surface area of a memory cell capacitor</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,657" target="_blank" rel="nofollow">7,776,657</a></td>
<td valign="top">Chip package thermal interface materials with dielectric obstructions for body-biasing, methods of using same, and systems containing same</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,651" target="_blank" rel="nofollow">7,776,651</a></td>
<td valign="top">Method for compensating for CTE mismatch using phase change lead-free super plastic solders</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,547" target="_blank" rel="nofollow">7,776,547</a></td>
<td valign="top">Cellular analysis using Raman surface scanning</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 12 August 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-12-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-12-august-2010/#comments</comments>
		<pubDate>Thu, 12 Aug 2010 12:39:25 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10116</guid>
		<description><![CDATA[1 US patent application published on 12 August 2010 and assigned to Intel



1
20100202550
SCALABLE SYSTEM TO ADAPTIVELY TRANSMIT AND RECEIVE INCLUDING ADAPTIVE ANTENNA SIGNAL AND BACK-END PROCESSORS


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 12 August 2010 and assigned to Intel<br />
<span id="more-10116"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202550.PGNR.&#038;OS=DN/20100202550RS=DN/20100202550" target="_blank">20100202550</a></td>
<td valign="top">SCALABLE SYSTEM TO ADAPTIVELY TRANSMIT AND RECEIVE INCLUDING ADAPTIVE ANTENNA SIGNAL AND BACK-END PROCESSORS</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
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		<item>
		<title>Intel patents granted on 10 August 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-10-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-10-august-2010/#comments</comments>
		<pubDate>Tue, 10 Aug 2010 13:49:23 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10076</guid>
		<description><![CDATA[37 US patents granted on 10 August 2010 and assigned to Intel



1
7,774,846
Method and apparatus for controlling data propagation


2
7,774,824
Multifactor device authentication


3
7,774,794
Method and system for managing bandwidth in a virtualized system


4
7,774,781
Storage subsystem access prioritization by system process and foreground application identification


5
7,774,769
Transmitting trace-specific information in a transformed application


6
7,774,766
Method and system for performing reassociation in software loops


7
7,774,764
Method and system [...]]]></description>
			<content:encoded><![CDATA[<p>37 US patents granted on 10 August 2010 and assigned to Intel<br />
<span id="more-10076"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,846" target="_blank" rel="nofollow">7,774,846</a></td>
<td valign="top">Method and apparatus for controlling data propagation</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,824" target="_blank" rel="nofollow">7,774,824</a></td>
<td valign="top">Multifactor device authentication</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,794" target="_blank" rel="nofollow">7,774,794</a></td>
<td valign="top">Method and system for managing bandwidth in a virtualized system</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,781" target="_blank" rel="nofollow">7,774,781</a></td>
<td valign="top">Storage subsystem access prioritization by system process and foreground application identification</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,769" target="_blank" rel="nofollow">7,774,769</a></td>
<td valign="top">Transmitting trace-specific information in a transformed application</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,766" target="_blank" rel="nofollow">7,774,766</a></td>
<td valign="top">Method and system for performing reassociation in software loops</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,764" target="_blank" rel="nofollow">7,774,764</a></td>
<td valign="top">Method and system for efficient range and stride checking</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,759" target="_blank" rel="nofollow">7,774,759</a></td>
<td valign="top">Methods and apparatus to detect a macroscopic transaction boundary in a program</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,684" target="_blank" rel="nofollow">7,774,684</a></td>
<td valign="top">Reliability, availability, and serviceability in a memory device</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,671" target="_blank" rel="nofollow">7,774,671</a></td>
<td valign="top">Method and apparatus to adjust voltage for storage location reliability</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,651" target="_blank" rel="nofollow">7,774,651</a></td>
<td valign="top">System and method to detect errors and predict potential failures</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,626" target="_blank" rel="nofollow">7,774,626</a></td>
<td valign="top">Method to control core duty cycles using low power modes</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,600" target="_blank" rel="nofollow">7,774,600</a></td>
<td valign="top">Launching a secure kernel in a multiprocessor system</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,590" target="_blank" rel="nofollow">7,774,590</a></td>
<td valign="top">Resiliently retaining state information of a many-core processor</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,575" target="_blank" rel="nofollow">7,774,575</a></td>
<td valign="top">Integrated circuit capable of mapping logical block address data across multiple domains</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,521" target="_blank" rel="nofollow">7,774,521</a></td>
<td valign="top">Method and apparatus for reducing power consumption for isochronous data transfers</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,520" target="_blank" rel="nofollow">7,774,520</a></td>
<td valign="top">Method and apparatus for maintaining synchronization of audio in a computing system</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,466" target="_blank" rel="nofollow">7,774,466</a></td>
<td valign="top">Methods and apparatus for load balancing storage nodes in a distributed storage area network system</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,325" target="_blank" rel="nofollow">7,774,325</a></td>
<td valign="top">Distributed network attached storage system</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,278" target="_blank" rel="nofollow">7,774,278</a></td>
<td valign="top">Wireless access unit with trunk interface</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,962" target="_blank" rel="nofollow">7,773,962</a></td>
<td valign="top">Method and apparatus for efficiently applying frequency correction</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,669" target="_blank" rel="nofollow">7,773,669</a></td>
<td valign="top">Cascaded phase pulse position and pulse width modulation based digital transmitter</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,632" target="_blank" rel="nofollow">7,773,632</a></td>
<td valign="top">Header compress/decompress framework</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,626" target="_blank" rel="nofollow">7,773,626</a></td>
<td valign="top">Technique to improve network switch throughput</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,620" target="_blank" rel="nofollow">7,773,620</a></td>
<td valign="top">Method, system, and program for overrun identification</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,564" target="_blank" rel="nofollow">7,773,564</a></td>
<td valign="top">Subscriber unit in a hybrid link incorporating spatial multiplexing</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,514" target="_blank" rel="nofollow">7,773,514</a></td>
<td valign="top">Resilient flow control systems and methods</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,504" target="_blank" rel="nofollow">7,773,504</a></td>
<td valign="top">Bandwidth allocation for network packet traffic</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,493" target="_blank" rel="nofollow">7,773,493</a></td>
<td valign="top">Probe-based storage device</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,034" target="_blank" rel="nofollow">7,773,034</a></td>
<td valign="top">Method for acquisition of GPS signals and GPS receiver with sample time error and frequency offset compensation</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,819" target="_blank" rel="nofollow">7,772,819</a></td>
<td valign="top">Systems and methods for improved coupled inductor topology efficiency utilizing a light load signal</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,708" target="_blank" rel="nofollow">7,772,708</a></td>
<td valign="top">Stacking integrated circuit dies</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,706" target="_blank" rel="nofollow">7,772,706</a></td>
<td valign="top">Air-gap ILD with unlanded vias</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,702" target="_blank" rel="nofollow">7,772,702</a></td>
<td valign="top">Dielectric spacers for metal interconnects and method to form the same</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,090" target="_blank" rel="nofollow">7,772,090</a></td>
<td valign="top">Methods for laser scribing wafers</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,771,661" target="_blank" rel="nofollow">7,771,661</a></td>
<td valign="top">Methods for uniform metal impregnation into a nanoporous material</td>
</tr>
<tr>
<td valign="top" align="right">37</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,630" target="_blank" rel="nofollow">7,770,630</a></td>
<td valign="top">Modular capillary pumped loop cooling system</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patent applications published on 05 August 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-05-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-05-august-2010/#comments</comments>
		<pubDate>Thu, 05 Aug 2010 13:42:24 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10037</guid>
		<description><![CDATA[1 US patent application published on 05 August 2010 and assigned to Intel



1
20100193173
HEAT SINKS AND METHOD OF FORMATION


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 05 August 2010 and assigned to Intel<br />
<span id="more-10037"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100193173.PGNR.&#038;OS=DN/20100193173RS=DN/20100193173" target="_blank">20100193173</a></td>
<td valign="top">HEAT SINKS AND METHOD OF FORMATION</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patents granted on 03 August 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-03-august-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-03-august-2010/#comments</comments>
		<pubDate>Tue, 03 Aug 2010 14:08:36 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9997</guid>
		<description><![CDATA[43 US patents granted on 03 August 2010 and assigned to Intel



1
7,770,162
Statement shifting to increase parallelism of loops


2
7,770,088
Techniques to transmit network protocol units


3
7,770,051
Strategy to verify asynchronous links across chips


4
7,770,034
Performance monitoring based dynamic voltage and frequency scaling


5
7,770,030
Content guard system for copy protection of recordable media


6
7,770,005
Launching a secure kernel in a multiprocessor system


7
7,770,003
Updating firmware securely over a [...]]]></description>
			<content:encoded><![CDATA[<p>43 US patents granted on 03 August 2010 and assigned to Intel<br />
<span id="more-9997"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,162" target="_blank" rel="nofollow">7,770,162</a></td>
<td valign="top">Statement shifting to increase parallelism of loops</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,088" target="_blank" rel="nofollow">7,770,088</a></td>
<td valign="top">Techniques to transmit network protocol units</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,051" target="_blank" rel="nofollow">7,770,051</a></td>
<td valign="top">Strategy to verify asynchronous links across chips</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,034" target="_blank" rel="nofollow">7,770,034</a></td>
<td valign="top">Performance monitoring based dynamic voltage and frequency scaling</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,030" target="_blank" rel="nofollow">7,770,030</a></td>
<td valign="top">Content guard system for copy protection of recordable media</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,005" target="_blank" rel="nofollow">7,770,005</a></td>
<td valign="top">Launching a secure kernel in a multiprocessor system</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,003" target="_blank" rel="nofollow">7,770,003</a></td>
<td valign="top">Updating firmware securely over a network</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,964" target="_blank" rel="nofollow">7,769,964</a></td>
<td valign="top">Technique to perform memory reference filtering</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,956" target="_blank" rel="nofollow">7,769,956</a></td>
<td valign="top">Pre-coherence channel</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,947" target="_blank" rel="nofollow">7,769,947</a></td>
<td valign="top">Management of data redundancy based on power availability in mobile computer systems</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,938" target="_blank" rel="nofollow">7,769,938</a></td>
<td valign="top">Processor selection for an interrupt identifying a processor cluster</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,924" target="_blank" rel="nofollow">7,769,924</a></td>
<td valign="top">Method and system for low latency audio-visual transport</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,918" target="_blank" rel="nofollow">7,769,918</a></td>
<td valign="top">Apparatus and method for high performance volatile disk drive memory access using an integrated DMA engine</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,883" target="_blank" rel="nofollow">7,769,883</a></td>
<td valign="top">Communicating message request transaction types between agents in a computer system using multiple message groups</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,868" target="_blank" rel="nofollow">7,769,868</a></td>
<td valign="top">Method and system for assigning client requests to a server</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,856" target="_blank" rel="nofollow">7,769,856</a></td>
<td valign="top">Automatic tuning of communication protocol performance</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,836" target="_blank" rel="nofollow">7,769,836</a></td>
<td valign="top">Method and apparatus for removable device modification of system configuration</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,109" target="_blank" rel="nofollow">7,769,109</a></td>
<td valign="top">Method and apparatus to perform modulation using integer timing relationships between intra symbol modulation components</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,107" target="_blank" rel="nofollow">7,769,107</a></td>
<td valign="top">Semi-blind analog beamforming for multiple-antenna systems</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,097" target="_blank" rel="nofollow">7,769,097</a></td>
<td valign="top">Methods and apparatus to control transmission of a multicarrier wireless communication channel through multiple antennas</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,048" target="_blank" rel="nofollow">7,769,048</a></td>
<td valign="top">Link and lane level packetization scheme of encoding in serial links</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,026" target="_blank" rel="nofollow">7,769,026</a></td>
<td valign="top">Efficient sort scheme for a hierarchical scheduler</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,002" target="_blank" rel="nofollow">7,769,002</a></td>
<td valign="top">Constrained dynamic path selection among multiple communication interfaces</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,988" target="_blank" rel="nofollow">7,768,988</a></td>
<td valign="top">Method and apparatus to perform network medium reservation in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,971" target="_blank" rel="nofollow">7,768,971</a></td>
<td valign="top">Central frequency modification without communication disruption</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,958" target="_blank" rel="nofollow">7,768,958</a></td>
<td valign="top">Flexible architecture for wireless communication networks</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,911" target="_blank" rel="nofollow">7,768,911</a></td>
<td valign="top">Platform-based method and apparatus for containing worms using multi-timescale heuristics</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,817" target="_blank" rel="nofollow">7,768,817</a></td>
<td valign="top">VCC control inside data register of memory device</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,518" target="_blank" rel="nofollow">7,768,518</a></td>
<td valign="top">Enabling multiple instruction stream/multiple data stream extensions on microprocessors</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,508" target="_blank" rel="nofollow">7,768,508</a></td>
<td valign="top">Convertible display</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,420" target="_blank" rel="nofollow">7,768,420</a></td>
<td valign="top">Operation and control of wireless appliance networks</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,126" target="_blank" rel="nofollow">7,768,126</a></td>
<td valign="top">Barrier formation and structure to use in semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,079" target="_blank" rel="nofollow">7,768,079</a></td>
<td valign="top">Transistors with high-k dielectric spacer liner to mitigate lateral oxide encroachement</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,074" target="_blank" rel="nofollow">7,768,074</a></td>
<td valign="top">Dual salicide integration for salicide through trench contacts and structures formed thereby</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,563" target="_blank" rel="nofollow">7,767,563</a></td>
<td valign="top">Method of forming a silicide layer on a thinned silicon wafer, and related semiconducting structure</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,560" target="_blank" rel="nofollow">7,767,560</a></td>
<td valign="top">Three dimensional strained quantum wells and three dimensional strained surface channels by Ge confinement method</td>
</tr>
<tr>
<td valign="top" align="right">37</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,519" target="_blank" rel="nofollow">7,767,519</a></td>
<td valign="top">One transistor/one capacitor dynamic random access memory (1T/1C DRAM) cell</td>
</tr>
<tr>
<td valign="top" align="right">38</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,509" target="_blank" rel="nofollow">7,767,509</a></td>
<td valign="top">Methods of forming a multilayer capping film to minimize differential heating in anneal processes</td>
</tr>
<tr>
<td valign="top" align="right">39</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,486" target="_blank" rel="nofollow">7,767,486</a></td>
<td valign="top">High-volume on-wafer heterogeneous packaging of optical interconnects</td>
</tr>
<tr>
<td valign="top" align="right">40</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,025" target="_blank" rel="nofollow">7,767,025</a></td>
<td valign="top">Nozzle array configuration to facilitate deflux process improvement in chip attach process</td>
</tr>
<tr>
<td valign="top" align="right">41</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,766,691" target="_blank" rel="nofollow">7,766,691</a></td>
<td valign="top">Land grid array (LGA) socket loading mechanism for mobile platforms</td>
</tr>
<tr>
<td valign="top" align="right">42</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,825" target="_blank" rel="nofollow">7,765,825</a></td>
<td valign="top">Apparatus and method for thermal management of a memory device</td>
</tr>
<tr>
<td valign="top" align="right">43</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,691" target="_blank" rel="nofollow">7,765,691</a></td>
<td valign="top">Method and apparatus for a printed circuit board using laser assisted metallization and patterning of a substrate</td>
</tr>
</table>
]]></content:encoded>
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		<title>Intel patent applications published on 29 July 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-29-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-29-july-2010/#comments</comments>
		<pubDate>Thu, 29 Jul 2010 14:46:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9957</guid>
		<description><![CDATA[1 US patent application published on 29 July 2010 and assigned to Intel



1
20100191997
PREDICT COMPUTING PLATFORM MEMORY POWER UTILIZATION


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 29 July 2010 and assigned to Intel<br />
<span id="more-9957"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100191997.PGNR.&#038;OS=DN/20100191997RS=DN/20100191997" target="_blank">20100191997</a></td>
<td valign="top">PREDICT COMPUTING PLATFORM MEMORY POWER UTILIZATION</td>
</tr>
</table>
]]></content:encoded>
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		<title>Intel patents granted on 27 July 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-27-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-27-july-2010/#comments</comments>
		<pubDate>Tue, 27 Jul 2010 14:12:45 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9917</guid>
		<description><![CDATA[23 US patents granted on 27 July 2010 and assigned to Intel



1
RE41,454
Camera having an adaptive gain control


2
7,765,599
Multimedia transmitter, multimedia receiver, multimedia transmission system, and method for securely transmitting multimedia content over a wireless link


3
7,765,544
Method, apparatus and system for improving security in a virtual machine host


4
7,765,526
Management of watchpoints in debuggers


5
7,765,440
Method and apparatus for OS independent platform [...]]]></description>
			<content:encoded><![CDATA[<p>23 US patents granted on 27 July 2010 and assigned to Intel<br />
<span id="more-9917"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=RE41,454" target="_blank" rel="nofollow">RE41,454</a></td>
<td valign="top">Camera having an adaptive gain control</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,599" target="_blank" rel="nofollow">7,765,599</a></td>
<td valign="top">Multimedia transmitter, multimedia receiver, multimedia transmission system, and method for securely transmitting multimedia content over a wireless link</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,544" target="_blank" rel="nofollow">7,765,544</a></td>
<td valign="top">Method, apparatus and system for improving security in a virtual machine host</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,526" target="_blank" rel="nofollow">7,765,526</a></td>
<td valign="top">Management of watchpoints in debuggers</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,440" target="_blank" rel="nofollow">7,765,440</a></td>
<td valign="top">Method and apparatus for OS independent platform recovery</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,409" target="_blank" rel="nofollow">7,765,409</a></td>
<td valign="top">Modular BIOS update mechanism</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,392" target="_blank" rel="nofollow">7,765,392</a></td>
<td valign="top">Method and apparatus for establishing processor as core root of trust for measurement</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,386" target="_blank" rel="nofollow">7,765,386</a></td>
<td valign="top">Scalable parallel pipeline floating-point unit for vector processing</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,366" target="_blank" rel="nofollow">7,765,366</a></td>
<td valign="top">Memory micro-tiling</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,352" target="_blank" rel="nofollow">7,765,352</a></td>
<td valign="top">Reducing core wake-up latency in a computer system</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,327" target="_blank" rel="nofollow">7,765,327</a></td>
<td valign="top">Intermediate driver having a fail-over function</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,323" target="_blank" rel="nofollow">7,765,323</a></td>
<td valign="top">Sink device addressing mechanism</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,316" target="_blank" rel="nofollow">7,765,316</a></td>
<td valign="top">Scheduling the uploading of information from a client to a server</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,750" target="_blank" rel="nofollow">7,764,750</a></td>
<td valign="top">Phase correlator for wireless receiver and method for correlating using phase-quantized signals</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,675" target="_blank" rel="nofollow">7,764,675</a></td>
<td valign="top">Peer-to-peer connection between switch fabric endpoint nodes</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,650" target="_blank" rel="nofollow">7,764,650</a></td>
<td valign="top">Mobile station and method for fast roaming with integrity protection and source authentication using a common protocol</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,514" target="_blank" rel="nofollow">7,764,514</a></td>
<td valign="top">Electromagnetic interference shielding for device cooling</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,499" target="_blank" rel="nofollow">7,764,499</a></td>
<td valign="top">Electromagnetically-actuated micropump for liquid metal alloy</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,943" target="_blank" rel="nofollow">7,763,943</a></td>
<td valign="top">Reducing external resistance of a multi-gate device by incorporation of a partial metallic fin</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,511" target="_blank" rel="nofollow">7,763,511</a></td>
<td valign="top">Dielectric barrier for nanocrystals</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,399" target="_blank" rel="nofollow">7,763,399</a></td>
<td valign="top">Removal of ionic residues or oxides and prevention of photo-induced defects, ionic crystal or oxide growth on photolithographic surfaces</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,395" target="_blank" rel="nofollow">7,763,395</a></td>
<td valign="top">Radiation stability of polymer pellicles</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,317" target="_blank" rel="nofollow">7,763,317</a></td>
<td valign="top">High K dielectric growth on metal triflate or trifluoroacetate terminated III-V semiconductor surfaces</td>
</tr>
</table>
]]></content:encoded>
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		<title>Intel patent applications published on 22 July 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-22-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-22-july-2010/#comments</comments>
		<pubDate>Thu, 22 Jul 2010 15:01:34 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9878</guid>
		<description><![CDATA[No US patent applications published on 22 July 2010 and assigned to Intel
]]></description>
			<content:encoded><![CDATA[<p>No US patent applications published on 22 July 2010 and assigned to Intel</p>
]]></content:encoded>
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		<title>Intel patents granted on 20 July 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-20-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-20-july-2010/#comments</comments>
		<pubDate>Tue, 20 Jul 2010 14:59:05 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9837</guid>
		<description><![CDATA[45 US patents granted on 20 July 2010 and assigned to Intel



1
7,761,874
Managing processing system power and performance based on utilization trends


2
7,761,775
Mode selection for data transmission in wireless communication channels based on statistical parameters


3
7,761,768
Techniques for reconfigurable decoder for a wireless system


4
7,761,753
Memory channel with bit lane fail-over


5
7,761,723
Processor temperature control interface


6
7,761,720
Mechanism for processor power state aware distribution of [...]]]></description>
			<content:encoded><![CDATA[<p>45 US patents granted on 20 July 2010 and assigned to Intel<br />
<span id="more-9837"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,874" target="_blank" rel="nofollow">7,761,874</a></td>
<td valign="top">Managing processing system power and performance based on utilization trends</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,775" target="_blank" rel="nofollow">7,761,775</a></td>
<td valign="top">Mode selection for data transmission in wireless communication channels based on statistical parameters</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,768" target="_blank" rel="nofollow">7,761,768</a></td>
<td valign="top">Techniques for reconfigurable decoder for a wireless system</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,753" target="_blank" rel="nofollow">7,761,753</a></td>
<td valign="top">Memory channel with bit lane fail-over</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,723" target="_blank" rel="nofollow">7,761,723</a></td>
<td valign="top">Processor temperature control interface</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,720" target="_blank" rel="nofollow">7,761,720</a></td>
<td valign="top">Mechanism for processor power state aware distribution of lowest priority interrupts</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,701" target="_blank" rel="nofollow">7,761,701</a></td>
<td valign="top">Component firmware integration in distributed systems</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,696" target="_blank" rel="nofollow">7,761,696</a></td>
<td valign="top">Quiescing and de-quiescing point-to-point links</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,694" target="_blank" rel="nofollow">7,761,694</a></td>
<td valign="top">Execution unit for performing shuffle and other operations</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,676" target="_blank" rel="nofollow">7,761,676</a></td>
<td valign="top">Protecting memory by containing pointer accesses</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,674" target="_blank" rel="nofollow">7,761,674</a></td>
<td valign="top">Identifier associated with memory locations for managing memory accesses</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,666" target="_blank" rel="nofollow">7,761,666</a></td>
<td valign="top">Temporally relevant data placement</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,529" target="_blank" rel="nofollow">7,761,529</a></td>
<td valign="top">Method, system, and program for managing memory requests by devices</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,515" target="_blank" rel="nofollow">7,761,515</a></td>
<td valign="top">Group intercom, delayed playback, and ad-hoc based communications system and method</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,327" target="_blank" rel="nofollow">7,761,327</a></td>
<td valign="top">Ensuring that advertisements are played</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,274" target="_blank" rel="nofollow">7,761,274</a></td>
<td valign="top">Temperature-based clock frequency controller apparatus and method</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,179" target="_blank" rel="nofollow">7,761,179</a></td>
<td valign="top">Method for consistent updates to automated process control (APC) models with partitioning along multiple components</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,761,057" target="_blank" rel="nofollow">7,761,057</a></td>
<td valign="top">Managing system clocks to reduce RFI</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,875" target="_blank" rel="nofollow">7,760,875</a></td>
<td valign="top">Accelerating Diffie-Hellman key-exchange protocol with zero-biased exponent windowing</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,873" target="_blank" rel="nofollow">7,760,873</a></td>
<td valign="top">Method and a system for a quick verification rabin signature scheme</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,830" target="_blank" rel="nofollow">7,760,830</a></td>
<td valign="top">Techniques to reduce the impact of jitter on communications system performance</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,804" target="_blank" rel="nofollow">7,760,804</a></td>
<td valign="top">Efficient use of a render cache</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,755" target="_blank" rel="nofollow">7,760,755</a></td>
<td valign="top">Method and device of adaptive control of data rate, fragmentation and request to send protection in wireless networks</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,694" target="_blank" rel="nofollow">7,760,694</a></td>
<td valign="top">Deviating from a transmission map to communicate in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,678" target="_blank" rel="nofollow">7,760,678</a></td>
<td valign="top">Cooperative transmission apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,676" target="_blank" rel="nofollow">7,760,676</a></td>
<td valign="top">Adaptive DRX cycle length based on available battery power</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,626" target="_blank" rel="nofollow">7,760,626</a></td>
<td valign="top">Load balancing and failover</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,500" target="_blank" rel="nofollow">7,760,500</a></td>
<td valign="top">Liquid cooling system</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,431" target="_blank" rel="nofollow">7,760,431</a></td>
<td valign="top">Method of and apparatus for modifying polarity of light</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,422" target="_blank" rel="nofollow">7,760,422</a></td>
<td valign="top">Semiconductor raman ring amplifier</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,214" target="_blank" rel="nofollow">7,760,214</a></td>
<td valign="top">Inserting transitions into a waveform that drives a display</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,140" target="_blank" rel="nofollow">7,760,140</a></td>
<td valign="top">Multiband antenna array using electromagnetic bandgap structures</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,121" target="_blank" rel="nofollow">7,760,121</a></td>
<td valign="top">Dual data weighted average dynamic element matching in analog-to-digital converters</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,037" target="_blank" rel="nofollow">7,760,037</a></td>
<td valign="top">Process, voltage, and temperature compensated clock generator</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,033" target="_blank" rel="nofollow">7,760,033</a></td>
<td valign="top">Ring oscillators for NMOS and PMOS source to drain leakage and gate leakage</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,780" target="_blank" rel="nofollow">7,759,780</a></td>
<td valign="top">Microelectronic package with wear resistant coating</td>
</tr>
<tr>
<td valign="top" align="right">37</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,774" target="_blank" rel="nofollow">7,759,774</a></td>
<td valign="top">Shielded structures to protect semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">38</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,262" target="_blank" rel="nofollow">7,759,262</a></td>
<td valign="top">Selective formation of dielectric etch stop layers</td>
</tr>
<tr>
<td valign="top" align="right">39</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,241" target="_blank" rel="nofollow">7,759,241</a></td>
<td valign="top">Group II element alloys for protecting metal interconnects</td>
</tr>
<tr>
<td valign="top" align="right">40</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,142" target="_blank" rel="nofollow">7,759,142</a></td>
<td valign="top">Quantum well MOSFET channels having uni-axial strain caused by metal source/drains, and conformal regrowth source/drains</td>
</tr>
<tr>
<td valign="top" align="right">41</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,028" target="_blank" rel="nofollow">7,759,028</a></td>
<td valign="top">Sub-resolution assist features</td>
</tr>
<tr>
<td valign="top" align="right">42</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,024" target="_blank" rel="nofollow">7,759,024</a></td>
<td valign="top">Controlling shape of a reticle with low friction film coating at backside</td>
</tr>
<tr>
<td valign="top" align="right">43</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,022" target="_blank" rel="nofollow">7,759,022</a></td>
<td valign="top">Phase shift mask structure and fabrication process</td>
</tr>
<tr>
<td valign="top" align="right">44</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,758,238" target="_blank" rel="nofollow">7,758,238</a></td>
<td valign="top">Temperature measurement with reduced extraneous infrared in a processing chamber</td>
</tr>
<tr>
<td valign="top" align="right">45</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,363" target="_blank" rel="nofollow">7,757,363</a></td>
<td valign="top">Support system for semiconductor wafers</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 15 July 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-15-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-15-july-2010/#comments</comments>
		<pubDate>Thu, 15 Jul 2010 15:49:47 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9797</guid>
		<description><![CDATA[No US patent applications published on 15 July 2010 and assigned to Intel
]]></description>
			<content:encoded><![CDATA[<p>No US patent applications published on 15 July 2010 and assigned to Intel</p>
]]></content:encoded>
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		<item>
		<title>Intel patents granted on 13 July 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-13-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-13-july-2010/#comments</comments>
		<pubDate>Tue, 13 Jul 2010 16:17:25 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9757</guid>
		<description><![CDATA[28 US patents granted on 13 July 2010 and assigned to Intel



1
7,757,238
Task switching with a task containing code region to adjust priority


2
7,757,231
System and method to deprivilege components of a virtual machine monitor


3
7,757,222
Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal


4
7,757,221
Apparatus and method for dynamic binary translator to support precise exceptions with [...]]]></description>
			<content:encoded><![CDATA[<p>28 US patents granted on 13 July 2010 and assigned to Intel<br />
<span id="more-9757"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,238" target="_blank" rel="nofollow">7,757,238</a></td>
<td valign="top">Task switching with a task containing code region to adjust priority</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,231" target="_blank" rel="nofollow">7,757,231</a></td>
<td valign="top">System and method to deprivilege components of a virtual machine monitor</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,222" target="_blank" rel="nofollow">7,757,222</a></td>
<td valign="top">Generating efficient parallel code using partitioning, coalescing, and degenerative loop and guard removal</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,221" target="_blank" rel="nofollow">7,757,221</a></td>
<td valign="top">Apparatus and method for dynamic binary translator to support precise exceptions with minimal optimization constraints</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,103" target="_blank" rel="nofollow">7,757,103</a></td>
<td valign="top">Method and apparatus to estimate energy consumed by central processing unit core</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,098" target="_blank" rel="nofollow">7,757,098</a></td>
<td valign="top">Method and apparatus for verifying authenticity of initial boot code</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,081" target="_blank" rel="nofollow">7,757,081</a></td>
<td valign="top">Launching a secure kernel in a multiprocessor system</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,065" target="_blank" rel="nofollow">7,757,065</a></td>
<td valign="top">Instruction segment recording scheme</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,046" target="_blank" rel="nofollow">7,757,046</a></td>
<td valign="top">Method and apparatus for optimizing line writes in cache coherent systems</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,045" target="_blank" rel="nofollow">7,757,045</a></td>
<td valign="top">Synchronizing recency information in an inclusive cache hierarchy</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,035" target="_blank" rel="nofollow">7,757,035</a></td>
<td valign="top">Method for optimizing virtualization technology and memory protections using processor-extensions for page table and page directory striping</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,020" target="_blank" rel="nofollow">7,757,020</a></td>
<td valign="top">Point-to-point link negotiation method and apparatus</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,947" target="_blank" rel="nofollow">7,756,947</a></td>
<td valign="top">Apparatus, systems, and methods to support service calls in an electronic service network</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,509" target="_blank" rel="nofollow">7,756,509</a></td>
<td valign="top">Methods and apparatus for providing an access profile system associated with a broadband wireless access network</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,495" target="_blank" rel="nofollow">7,756,495</a></td>
<td valign="top">High speed receiver</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,471" target="_blank" rel="nofollow">7,756,471</a></td>
<td valign="top">Systems and methods for multi-element antenna arrays with aperture control shutters</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,208" target="_blank" rel="nofollow">7,756,208</a></td>
<td valign="top">Multicarrier communication system and methods for communicating with subscriber stations of different bandwidth profiles</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,103" target="_blank" rel="nofollow">7,756,103</a></td>
<td valign="top">Device, system and method of adjustment of a delivery mechanism according to access categories</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,756,053" target="_blank" rel="nofollow">7,756,053</a></td>
<td valign="top">Memory agent with error hardware</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,881" target="_blank" rel="nofollow">7,755,881</a></td>
<td valign="top">Modular server architecture with Ethernet routed across a backplane utilizing an integrated Ethernet switch module</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,650" target="_blank" rel="nofollow">7,755,650</a></td>
<td valign="top">Illumination modulation technique</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,628" target="_blank" rel="nofollow">7,755,628</a></td>
<td valign="top">Method and apparatus for multi-level ray tracing</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,186" target="_blank" rel="nofollow">7,755,186</a></td>
<td valign="top">Cooling solutions for die-down integrated circuit packages</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,165" target="_blank" rel="nofollow">7,755,165</a></td>
<td valign="top">iTFC with optimized C(T)</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,140" target="_blank" rel="nofollow">7,755,140</a></td>
<td valign="top">Process charging and electrostatic damage protection in silicon-on-insulator technology</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,124" target="_blank" rel="nofollow">7,755,124</a></td>
<td valign="top">Laminating magnetic materials in a semiconductor device</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,082" target="_blank" rel="nofollow">7,755,082</a></td>
<td valign="top">Forming self-aligned nano-electrodes</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,552" target="_blank" rel="nofollow">7,754,552</a></td>
<td valign="top">Preventing silicide formation at the gate electrode in a replacement metal gate technology</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 08 July 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-08-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-08-july-2010/#comments</comments>
		<pubDate>Thu, 08 Jul 2010 13:55:57 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9717</guid>
		<description><![CDATA[3 US patent applications published on 08 July 2010 and assigned to Intel



1
20100174965
LDPC CODES WITH SMALL AMOUNT OF WIRING


2
20100172318
Handling Hybrid Automatic Repeat Requests in Wireless Systems


3
20100171950
METHODS FOR UNIFORM METAL IMPREGNATION INTO A NANOPOROUS MATERIAL


]]></description>
			<content:encoded><![CDATA[<p>3 US patent applications published on 08 July 2010 and assigned to Intel<br />
<span id="more-9717"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100174965.PGNR.&#038;OS=DN/20100174965RS=DN/20100174965" target="_blank">20100174965</a></td>
<td valign="top">LDPC CODES WITH SMALL AMOUNT OF WIRING</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100172318.PGNR.&#038;OS=DN/20100172318RS=DN/20100172318" target="_blank">20100172318</a></td>
<td valign="top">Handling Hybrid Automatic Repeat Requests in Wireless Systems</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171950.PGNR.&#038;OS=DN/20100171950RS=DN/20100171950" target="_blank">20100171950</a></td>
<td valign="top">METHODS FOR UNIFORM METAL IMPREGNATION INTO A NANOPOROUS MATERIAL</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 06 July 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-06-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-06-july-2010/#comments</comments>
		<pubDate>Tue, 06 Jul 2010 14:41:22 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9678</guid>
		<description><![CDATA[44 US patents granted on 06 July 2010 and assigned to Intel



1
7,752,635
System and method for configuring a virtual network interface card


2
7,752,613
Disambiguation in dynamic binary translation


3
7,752,611
Speculative code motion for memory latency hiding


4
7,752,520
Apparatus and method capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes


5
7,752,473
Providing a deterministic idle time window for an idle [...]]]></description>
			<content:encoded><![CDATA[<p>44 US patents granted on 06 July 2010 and assigned to Intel<br />
<span id="more-9678"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,635" target="_blank" rel="nofollow">7,752,635</a></td>
<td valign="top">System and method for configuring a virtual network interface card</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,613" target="_blank" rel="nofollow">7,752,613</a></td>
<td valign="top">Disambiguation in dynamic binary translation</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,611" target="_blank" rel="nofollow">7,752,611</a></td>
<td valign="top">Speculative code motion for memory latency hiding</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,520" target="_blank" rel="nofollow">7,752,520</a></td>
<td valign="top">Apparatus and method capable of a unified quasi-cyclic low-density parity-check structure for variable code rates and sizes</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,473" target="_blank" rel="nofollow">7,752,473</a></td>
<td valign="top">Providing a deterministic idle time window for an idle state of a device</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,468" target="_blank" rel="nofollow">7,752,468</a></td>
<td valign="top">Predict computing platform memory power utilization</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,436" target="_blank" rel="nofollow">7,752,436</a></td>
<td valign="top">Exclusive access for secure audio program</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,428" target="_blank" rel="nofollow">7,752,428</a></td>
<td valign="top">System and method for trusted early boot flow</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,423" target="_blank" rel="nofollow">7,752,423</a></td>
<td valign="top">Avoiding execution of instructions in a second processor by committing results obtained from speculative execution of the instructions in a first processor</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,411" target="_blank" rel="nofollow">7,752,411</a></td>
<td valign="top">Chips providing single and consolidated commands</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,397" target="_blank" rel="nofollow">7,752,397</a></td>
<td valign="top">Repeated conflict acknowledgements in a cache coherency protocol</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,030" target="_blank" rel="nofollow">7,752,030</a></td>
<td valign="top">Virtualization as emulation support</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,994" target="_blank" rel="nofollow">7,751,994</a></td>
<td valign="top">Intelligent battery safety management system configured to compare collected operational data with reference operational data</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,858" target="_blank" rel="nofollow">7,751,858</a></td>
<td valign="top">Sleep-mode statistics apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,854" target="_blank" rel="nofollow">7,751,854</a></td>
<td valign="top">Null deepening for an adaptive antenna based communication station</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,794" target="_blank" rel="nofollow">7,751,794</a></td>
<td valign="top">Apparatus, system and method capable of integrating a cellular phone stack in an extended firmware interface (EFI) layer</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,777" target="_blank" rel="nofollow">7,751,777</a></td>
<td valign="top">System and method for transmitting data in a communication network</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,719" target="_blank" rel="nofollow">7,751,719</a></td>
<td valign="top">Electrical generation of return-to-zero (RZ) data pattern with flexible duty cycle adjustment for optical transmission</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,589" target="_blank" rel="nofollow">7,751,589</a></td>
<td valign="top">Three-dimensional road map estimation from video sequences by tracking pedestrians</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,584" target="_blank" rel="nofollow">7,751,584</a></td>
<td valign="top">Method to provide transparent information in binary drivers via steganographic techniques</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,442" target="_blank" rel="nofollow">7,751,442</a></td>
<td valign="top">Serial ethernet device-to-device interconnection</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,440" target="_blank" rel="nofollow">7,751,440</a></td>
<td valign="top">Reconfigurable frame parser</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,422" target="_blank" rel="nofollow">7,751,422</a></td>
<td valign="top">Group tag caching of memory contents</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,402" target="_blank" rel="nofollow">7,751,402</a></td>
<td valign="top">Method and apparatus for gigabit packet assignment for multithreaded packet processing</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,378" target="_blank" rel="nofollow">7,751,378</a></td>
<td valign="top">Method, apparatus and system for client-based distributed PBX for enterprise telephony</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,368" target="_blank" rel="nofollow">7,751,368</a></td>
<td valign="top">Providing CQI feedback to a transmitter station in a closed-loop MIMO system</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,333" target="_blank" rel="nofollow">7,751,333</a></td>
<td valign="top">Method and apparatus to couple a module to a management controller on an interconnect</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,274" target="_blank" rel="nofollow">7,751,274</a></td>
<td valign="top">Extended synchronized clock</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,251" target="_blank" rel="nofollow">7,751,251</a></td>
<td valign="top">Current sensing scheme for non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,226" target="_blank" rel="nofollow">7,751,226</a></td>
<td valign="top">Reading phase change memories with select devices</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,189" target="_blank" rel="nofollow">7,751,189</a></td>
<td valign="top">Cooling arrangement to cool components on circuit board</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,914" target="_blank" rel="nofollow">7,750,914</a></td>
<td valign="top">Subdividing geometry images in graphics hardware</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,739" target="_blank" rel="nofollow">7,750,739</a></td>
<td valign="top">Dual reactive shunt low noise amplifier</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,629" target="_blank" rel="nofollow">7,750,629</a></td>
<td valign="top">Measuring electric and magnetic field</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,487" target="_blank" rel="nofollow">7,750,487</a></td>
<td valign="top">Metal-metal bonding of compliant interconnect</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,471" target="_blank" rel="nofollow">7,750,471</a></td>
<td valign="top">Metal and alloy silicides on a single silicon wafer</td>
</tr>
<tr>
<td valign="top" align="right">37</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,466" target="_blank" rel="nofollow">7,750,466</a></td>
<td valign="top">Microelectronic assembly having second level interconnects including solder joints reinforced with crack arrester elements and method of forming same</td>
</tr>
<tr>
<td valign="top" align="right">38</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,450" target="_blank" rel="nofollow">7,750,450</a></td>
<td valign="top">Stacked die package with stud spacers</td>
</tr>
<tr>
<td valign="top" align="right">39</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,441" target="_blank" rel="nofollow">7,750,441</a></td>
<td valign="top">Conductive interconnects along the edge of a microelectronic device</td>
</tr>
<tr>
<td valign="top" align="right">40</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,433" target="_blank" rel="nofollow">7,750,433</a></td>
<td valign="top">Probe-based memory</td>
</tr>
<tr>
<td valign="top" align="right">41</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,333" target="_blank" rel="nofollow">7,750,333</a></td>
<td valign="top">Bit-erasing architecture for seek-scan probe (SSP) memory storage</td>
</tr>
<tr>
<td valign="top" align="right">42</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,906" target="_blank" rel="nofollow">7,749,906</a></td>
<td valign="top">Using unstable nitrides to form semiconductor structures</td>
</tr>
<tr>
<td valign="top" align="right">43</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,900" target="_blank" rel="nofollow">7,749,900</a></td>
<td valign="top">Method and core materials for semiconductor packaging</td>
</tr>
<tr>
<td valign="top" align="right">44</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,748,229" target="_blank" rel="nofollow">7,748,229</a></td>
<td valign="top">Liquid cooling system</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 01 July 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-01-july-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-01-july-2010/#comments</comments>
		<pubDate>Thu, 01 Jul 2010 13:52:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9638</guid>
		<description><![CDATA[5 US patent applications published on 01 July 2010 and assigned to Intel



1
20100169502
Hybrid method for delivering streaming media within the home


2
20100169155
Widget Development Tool


3
20100165206
Method and apparatus for noise reduction in video


4
20100164953
Systems and methods for transporting physical objects from real physical life into virtual worlds


5
20100164802
Arrangements for beam refinement in a wireless network


]]></description>
			<content:encoded><![CDATA[<p>5 US patent applications published on 01 July 2010 and assigned to Intel<br />
<span id="more-9638"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100169502.PGNR.&#038;OS=DN/20100169502RS=DN/20100169502" target="_blank">20100169502</a></td>
<td valign="top">Hybrid method for delivering streaming media within the home</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100169155.PGNR.&#038;OS=DN/20100169155RS=DN/20100169155" target="_blank">20100169155</a></td>
<td valign="top">Widget Development Tool</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100165206.PGNR.&#038;OS=DN/20100165206RS=DN/20100165206" target="_blank">20100165206</a></td>
<td valign="top">Method and apparatus for noise reduction in video</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100164953.PGNR.&#038;OS=DN/20100164953RS=DN/20100164953" target="_blank">20100164953</a></td>
<td valign="top">Systems and methods for transporting physical objects from real physical life into virtual worlds</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100164802.PGNR.&#038;OS=DN/20100164802RS=DN/20100164802" target="_blank">20100164802</a></td>
<td valign="top">Arrangements for beam refinement in a wireless network</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patents granted on 29 June 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-29-june-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-29-june-2010/#comments</comments>
		<pubDate>Tue, 29 Jun 2010 14:27:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9596</guid>
		<description><![CDATA[35 US patents granted on 29 June 2010 and assigned to Intel



1
7,748,037
Validating a memory type modification attempt


2
7,748,001
Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time


3
7,747,992
Methods and apparatus for creating software basic block layouts


4
7,747,932
Reducing the uncorrectable error rate in a lockstepped dual-modular [...]]]></description>
			<content:encoded><![CDATA[<p>35 US patents granted on 29 June 2010 and assigned to Intel<br />
<span id="more-9596"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,748,037" target="_blank" rel="nofollow">7,748,037</a></td>
<td valign="top">Validating a memory type modification attempt</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,748,001" target="_blank" rel="nofollow">7,748,001</a></td>
<td valign="top">Multi-thread processing system for detecting and handling live-lock conditions by arbitrating livelock priority of logical processors based on a predertermined amount of time</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,992" target="_blank" rel="nofollow">7,747,992</a></td>
<td valign="top">Methods and apparatus for creating software basic block layouts</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,932" target="_blank" rel="nofollow">7,747,932</a></td>
<td valign="top">Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,913" target="_blank" rel="nofollow">7,747,913</a></td>
<td valign="top">Correcting intermittent errors in data storage structures</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,897" target="_blank" rel="nofollow">7,747,897</a></td>
<td valign="top">Method and apparatus for lockstep processing on a fixed-latency interconnect</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,888" target="_blank" rel="nofollow">7,747,888</a></td>
<td valign="top">Technique to create link determinism</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,862" target="_blank" rel="nofollow">7,747,862</a></td>
<td valign="top">Method and apparatus to authenticate base and subscriber stations and secure sessions for broadband wireless networks</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,846" target="_blank" rel="nofollow">7,747,846</a></td>
<td valign="top">Managed redundant enterprise basic input/output system store update</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,788" target="_blank" rel="nofollow">7,747,788</a></td>
<td valign="top">Hardware oriented target-side native command queuing tag management</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,669" target="_blank" rel="nofollow">7,747,669</a></td>
<td valign="top">Rounding of binary integers</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,292" target="_blank" rel="nofollow">7,747,292</a></td>
<td valign="top">Techniques for adaptive interference cancellation</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,122" target="_blank" rel="nofollow">7,747,122</a></td>
<td valign="top">Method and apparatus for high speed silicon optical modulation using PN diode</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,078" target="_blank" rel="nofollow">7,747,078</a></td>
<td valign="top">Substring detection system and method</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,020" target="_blank" rel="nofollow">7,747,020</a></td>
<td valign="top">Technique for implementing a security algorithm</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,967" target="_blank" rel="nofollow">7,746,967</a></td>
<td valign="top">Beam-former and combiner for a multiple-antenna system</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,896" target="_blank" rel="nofollow">7,746,896</a></td>
<td valign="top">Base station and method for allocating bandwidth in a broadband wireless network with reduced latency</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,866" target="_blank" rel="nofollow">7,746,866</a></td>
<td valign="top">Ordered and duplicate-free delivery of wireless data frames</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,865" target="_blank" rel="nofollow">7,746,865</a></td>
<td valign="top">Maskable content addressable memory</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,856" target="_blank" rel="nofollow">7,746,856</a></td>
<td valign="top">Method, apparatus and system for optimizing packet throughput for content processing systems on chips</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,847" target="_blank" rel="nofollow">7,746,847</a></td>
<td valign="top">Jitter buffer management in a packet-based network</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,827" target="_blank" rel="nofollow">7,746,827</a></td>
<td valign="top">Methods and arrangements for selection of a wireless transmission method based upon signal to noise ratios</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,822" target="_blank" rel="nofollow">7,746,822</a></td>
<td valign="top">Dynamic multi-access relaying for wireless networks</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,810" target="_blank" rel="nofollow">7,746,810</a></td>
<td valign="top">Wake on wireless network techniques</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,795" target="_blank" rel="nofollow">7,746,795</a></td>
<td valign="top">Method, system, and apparatus for loopback parameter exchange</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,778" target="_blank" rel="nofollow">7,746,778</a></td>
<td valign="top">Resource based data rate control</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,689" target="_blank" rel="nofollow">7,746,689</a></td>
<td valign="top">Molecular quantum memory</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,135" target="_blank" rel="nofollow">7,746,135</a></td>
<td valign="top">Wake-up circuit</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,940" target="_blank" rel="nofollow">7,745,940</a></td>
<td valign="top">Forming ultra dense 3-D interconnect structures</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,917" target="_blank" rel="nofollow">7,745,917</a></td>
<td valign="top">Compliant integrated circuit package substrate</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,912" target="_blank" rel="nofollow">7,745,912</a></td>
<td valign="top">Stress absorption layer and cylinder solder joint method and apparatus</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,270" target="_blank" rel="nofollow">7,745,270</a></td>
<td valign="top">Tri-gate patterning using dual layer gate stack</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,013" target="_blank" rel="nofollow">7,745,013</a></td>
<td valign="top">Solder foams, nano-porous solders, foamed-solder bumps in chip packages, methods of assembling same, and systems containing same</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,744,816" target="_blank" rel="nofollow">7,744,816</a></td>
<td valign="top">Methods and device for biomolecule characterization</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,744,802" target="_blank" rel="nofollow">7,744,802</a></td>
<td valign="top">Dielectric film with low coefficient of thermal expansion (CTE) using liquid crystalline resin</td>
</tr>
</table>
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