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	<title>Latest Patents &#187; Intel</title>
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	<link>http://www.latestpatents.com</link>
	<description>Latest Patents of Leading Technology Companies</description>
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		<title>Intel patent applications published on 11 March 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-11-march-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-11-march-2010/#comments</comments>
		<pubDate>Thu, 11 Mar 2010 15:35:34 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8336</guid>
		<description><![CDATA[1 US patent application published on 11 March 2010 and assigned to Intel



1
20100061377
FLEXIBLE AND EXTENSIBLE RECEIVE SIDE SCALING


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 11 March 2010 and assigned to Intel<br />
<span id="more-8336"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100061377.PGNR.&#038;OS=DN/20100061377RS=DN/20100061377" target="_blank">20100061377</a></td>
<td valign="top">FLEXIBLE AND EXTENSIBLE RECEIVE SIDE SCALING</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 09 March 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-09-march-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-09-march-2010/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 17:34:42 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8297</guid>
		<description><![CDATA[22 US patents granted on 09 March 2010 and assigned to Intel



1
7,676,800
Method and apparatus for reducing the storage overhead of portable executable (PE) images


2
7,676,796
Device, system and method for maintaining a pre-defined number of free registers within an instrumented program


3
7,676,733
Techniques to perform forward error correction for an electrical backplane


4
7,676,665
Arrangements for initialization-time and run-time integration of firmware [...]]]></description>
			<content:encoded><![CDATA[<p>22 US patents granted on 09 March 2010 and assigned to Intel<br />
<span id="more-8297"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,800" target="_blank" rel="nofollow">7,676,800</a></td>
<td valign="top">Method and apparatus for reducing the storage overhead of portable executable (PE) images</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,796" target="_blank" rel="nofollow">7,676,796</a></td>
<td valign="top">Device, system and method for maintaining a pre-defined number of free registers within an instrumented program</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,733" target="_blank" rel="nofollow">7,676,733</a></td>
<td valign="top">Techniques to perform forward error correction for an electrical backplane</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,665" target="_blank" rel="nofollow">7,676,665</a></td>
<td valign="top">Arrangements for initialization-time and run-time integration of firmware and software extensions for supporting add-in hardware</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,654" target="_blank" rel="nofollow">7,676,654</a></td>
<td valign="top">Extended register space apparatus and methods for processors</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,604" target="_blank" rel="nofollow">7,676,604</a></td>
<td valign="top">Task context direct indexing in a protocol engine</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,603" target="_blank" rel="nofollow">7,676,603</a></td>
<td valign="top">Write combining protocol between processors and chipsets</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,595" target="_blank" rel="nofollow">7,676,595</a></td>
<td valign="top">Anycast addressing for internet protocol version six</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,535" target="_blank" rel="nofollow">7,676,535</a></td>
<td valign="top">Enhanced floating-point unit for extended functions</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,231" target="_blank" rel="nofollow">7,676,231</a></td>
<td valign="top">Methods and apparatus for selecting communication channels based on channel load information</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,197" target="_blank" rel="nofollow">7,676,197</a></td>
<td valign="top">Signal spectrum steering method, apparatus, and system</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,105" target="_blank" rel="nofollow">7,676,105</a></td>
<td valign="top">Method, apparatus, article and system for use in association with images</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,103" target="_blank" rel="nofollow">7,676,103</a></td>
<td valign="top">Enhancing video sharpness and contrast by luminance and chrominance transient improvement</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,027" target="_blank" rel="nofollow">7,676,027</a></td>
<td valign="top">Systems and methods to send and receive encrypted DTMF digits in a data flow</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,999" target="_blank" rel="nofollow">7,675,999</a></td>
<td valign="top">Multicarrier receiver and method with phase noise reduced signal</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,928" target="_blank" rel="nofollow">7,675,928</a></td>
<td valign="top">Increasing cache hits in network processors using flow-based packet assignment to compute engines</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,871" target="_blank" rel="nofollow">7,675,871</a></td>
<td valign="top">Split transaction protocol for a bus system</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,792" target="_blank" rel="nofollow">7,675,792</a></td>
<td valign="top">Generating reference currents compensated for process variation in non-volatile memories</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,182" target="_blank" rel="nofollow">7,675,182</a></td>
<td valign="top">Die warpage control</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,160" target="_blank" rel="nofollow">7,675,160</a></td>
<td valign="top">Individual sub-assembly containing a ceramic interposer, silicon voltage regulator, and array capacitor</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,729" target="_blank" rel="nofollow">7,674,729</a></td>
<td valign="top">Method and apparatus for imprinting a circuit pattern using ultrasonic vibrations</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,390" target="_blank" rel="nofollow">7,674,390</a></td>
<td valign="top">Zeolite&#8211;sol gel nano-composite low k dielectric</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/intel-patents-granted-on-09-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patent applications published on 04 March 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-04-march-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-04-march-2010/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 17:15:03 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8258</guid>
		<description><![CDATA[3 US patent applications published on 04 March 2010 and assigned to Intel



1
20100058336
ASSIGNMENT, AT LEAST IN PART, OF AT LEAST ONE VIRTUAL MACHINE TO AT LEAST ONE PACKET


2
20100056154
SYSTEM AND METHOD FOR RELOCATING A FOREIGN AGENT FOR AN IDLE MODE MOBILE STATION IN A PROXY MOBILE INTERNET PROTOCOL ENABLED ACCESS SERVICE NETWORK


3
20100053655
ERROR DIFFUSION-BASED IMAGE PROCESSING


]]></description>
			<content:encoded><![CDATA[<p>3 US patent applications published on 04 March 2010 and assigned to Intel<br />
<span id="more-8258"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100058336.PGNR.&#038;OS=DN/20100058336RS=DN/20100058336" target="_blank">20100058336</a></td>
<td valign="top">ASSIGNMENT, AT LEAST IN PART, OF AT LEAST ONE VIRTUAL MACHINE TO AT LEAST ONE PACKET</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100056154.PGNR.&#038;OS=DN/20100056154RS=DN/20100056154" target="_blank">20100056154</a></td>
<td valign="top">SYSTEM AND METHOD FOR RELOCATING A FOREIGN AGENT FOR AN IDLE MODE MOBILE STATION IN A PROXY MOBILE INTERNET PROTOCOL ENABLED ACCESS SERVICE NETWORK</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100053655.PGNR.&#038;OS=DN/20100053655RS=DN/20100053655" target="_blank">20100053655</a></td>
<td valign="top">ERROR DIFFUSION-BASED IMAGE PROCESSING</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/intel-patent-applications-published-on-04-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 02 March 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-02-march-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-02-march-2010/#comments</comments>
		<pubDate>Tue, 02 Mar 2010 18:07:12 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8218</guid>
		<description><![CDATA[36 US patents granted on 02 March 2010 and assigned to Intel



1
7,673,345
Providing extended memory protection


2
7,673,254
Apparatus, system and method for context and language specific data entry


3
7,673,170
Personal computer bus protocol with error correction mode


4
7,673,129
Secure booting from a memory device


5
7,673,128
Methods and apparatus to facilitate fast restarts in processor systems


6
7,673,126
Methods and apparatus to self-initialize a processor


7
7,673,113
Method for dynamic load [...]]]></description>
			<content:encoded><![CDATA[<p>36 US patents granted on 02 March 2010 and assigned to Intel<br />
<span id="more-8218"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,345" target="_blank" rel="nofollow">7,673,345</a></td>
<td valign="top">Providing extended memory protection</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,254" target="_blank" rel="nofollow">7,673,254</a></td>
<td valign="top">Apparatus, system and method for context and language specific data entry</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,170" target="_blank" rel="nofollow">7,673,170</a></td>
<td valign="top">Personal computer bus protocol with error correction mode</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,129" target="_blank" rel="nofollow">7,673,129</a></td>
<td valign="top">Secure booting from a memory device</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,128" target="_blank" rel="nofollow">7,673,128</a></td>
<td valign="top">Methods and apparatus to facilitate fast restarts in processor systems</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,126" target="_blank" rel="nofollow">7,673,126</a></td>
<td valign="top">Methods and apparatus to self-initialize a processor</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,113" target="_blank" rel="nofollow">7,673,113</a></td>
<td valign="top">Method for dynamic load balancing on partitioned systems</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,111" target="_blank" rel="nofollow">7,673,111</a></td>
<td valign="top">Memory system with both single and consolidated commands</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,090" target="_blank" rel="nofollow">7,673,090</a></td>
<td valign="top">Hot plug interface control method and apparatus</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,073" target="_blank" rel="nofollow">7,673,073</a></td>
<td valign="top">Multiphase encoded protocol and synchronization of buses</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,041" target="_blank" rel="nofollow">7,673,041</a></td>
<td valign="top">Method to perform exact string match in the data plane of a network processor</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,026" target="_blank" rel="nofollow">7,673,026</a></td>
<td valign="top">Speed sensitive content delivery in a client-server network</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,657" target="_blank" rel="nofollow">7,672,657</a></td>
<td valign="top">Tunable filter apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,653" target="_blank" rel="nofollow">7,672,653</a></td>
<td valign="top">Removing interfering signals in a broadband radio frequency receiver</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,529" target="_blank" rel="nofollow">7,672,529</a></td>
<td valign="top">Techniques to detect Gaussian noise</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,407" target="_blank" rel="nofollow">7,672,407</a></td>
<td valign="top">Mitigation of interference from periodic noise</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,387" target="_blank" rel="nofollow">7,672,387</a></td>
<td valign="top">Multiple input, multiple output wireless communication system, associated methods and data structures</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,372" target="_blank" rel="nofollow">7,672,372</a></td>
<td valign="top">Method and system for data management in a video decoder</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,365" target="_blank" rel="nofollow">7,672,365</a></td>
<td valign="top">Apparatus and methods for communicating using symbol-modulated subcarriers</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,335" target="_blank" rel="nofollow">7,672,335</a></td>
<td valign="top">Non-integer word size translation through rotation of different buffer alignment channels</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,178" target="_blank" rel="nofollow">7,672,178</a></td>
<td valign="top">Dynamic adaptive read return of DRAM data</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,132" target="_blank" rel="nofollow">7,672,132</a></td>
<td valign="top">Electronic packaging apparatus and method</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,120" target="_blank" rel="nofollow">7,672,120</a></td>
<td valign="top">Interchangeable keyboard for computer systems</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,865" target="_blank" rel="nofollow">7,671,865</a></td>
<td valign="top">Refresh of display</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,694" target="_blank" rel="nofollow">7,671,694</a></td>
<td valign="top">Programmable passive equalizer</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,471" target="_blank" rel="nofollow">7,671,471</a></td>
<td valign="top">Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,456" target="_blank" rel="nofollow">7,671,456</a></td>
<td valign="top">Power management integrated circuit</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,414" target="_blank" rel="nofollow">7,671,414</a></td>
<td valign="top">Semiconductor on insulator apparatus</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,358" target="_blank" rel="nofollow">7,671,358</a></td>
<td valign="top">Plasma implantated impurities in junction region recesses</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,120" target="_blank" rel="nofollow">7,671,120</a></td>
<td valign="top">Chain extension for thermal materials</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,951" target="_blank" rel="nofollow">7,670,951</a></td>
<td valign="top">Grid array connection device and method</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,928" target="_blank" rel="nofollow">7,670,928</a></td>
<td valign="top">Ultra-thin oxide bonding for S1 to S1 dual orientation bonding</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,919" target="_blank" rel="nofollow">7,670,919</a></td>
<td valign="top">Integrated capacitors in package-level structures, processes of making same, and systems containing same</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,894" target="_blank" rel="nofollow">7,670,894</a></td>
<td valign="top">Selective high-k dielectric film deposition for semiconductor device</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,866" target="_blank" rel="nofollow">7,670,866</a></td>
<td valign="top">Multi-die molded substrate integrated circuit device</td>
</tr>
<tr>
<td valign="top" align="right">36</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,167" target="_blank" rel="nofollow">7,670,167</a></td>
<td valign="top">Socket that engages a pin grid array</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 25 February 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-25-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-25-february-2010/#comments</comments>
		<pubDate>Thu, 25 Feb 2010 14:29:54 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8179</guid>
		<description><![CDATA[2 US patent applications published on 25 February 2010 and assigned to Intel



1
20100046671
OFDM RECEIVER AND METHODS FOR OPERATING IN HIGH-THROUGHPUT AND INCREASED RANGE MODES


2
20100045261
DESIGN FOR TESTABILITY TECHNIQUE FOR PHASE DETECTORS USED IN DIGITAL FEEDBACK DELAY LOCKED LOOPS


]]></description>
			<content:encoded><![CDATA[<p>2 US patent applications published on 25 February 2010 and assigned to Intel<br />
<span id="more-8179"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046671.PGNR.&#038;OS=DN/20100046671RS=DN/20100046671" target="_blank">20100046671</a></td>
<td valign="top">OFDM RECEIVER AND METHODS FOR OPERATING IN HIGH-THROUGHPUT AND INCREASED RANGE MODES</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100045261.PGNR.&#038;OS=DN/20100045261RS=DN/20100045261" target="_blank">20100045261</a></td>
<td valign="top">DESIGN FOR TESTABILITY TECHNIQUE FOR PHASE DETECTORS USED IN DIGITAL FEEDBACK DELAY LOCKED LOOPS</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patents granted on 23 February 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-23-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-23-february-2010/#comments</comments>
		<pubDate>Tue, 23 Feb 2010 13:46:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8141</guid>
		<description><![CDATA[35 US patents granted on 23 February 2010 and assigned to Intel



1
7,669,242
Agent presence monitor configured to execute in a secure environment


2
7,669,229
Network protecting authentication proxy


3
7,669,203
Virtual multithreading translation mechanism including retrofit capability


4
7,669,069
Control of link supply power based on link port mode


5
7,669,009
Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches


6
7,668,958
Method for discovery [...]]]></description>
			<content:encoded><![CDATA[<p>35 US patents granted on 23 February 2010 and assigned to Intel<br />
<span id="more-8141"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,242" target="_blank" rel="nofollow">7,669,242</a></td>
<td valign="top">Agent presence monitor configured to execute in a secure environment</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,229" target="_blank" rel="nofollow">7,669,229</a></td>
<td valign="top">Network protecting authentication proxy</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,203" target="_blank" rel="nofollow">7,669,203</a></td>
<td valign="top">Virtual multithreading translation mechanism including retrofit capability</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,069" target="_blank" rel="nofollow">7,669,069</a></td>
<td valign="top">Control of link supply power based on link port mode</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,009" target="_blank" rel="nofollow">7,669,009</a></td>
<td valign="top">Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,958" target="_blank" rel="nofollow">7,668,958</a></td>
<td valign="top">Method for discovery and routing using a priori knowledge in the form of application programme within mobile AD-HOC networks</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,948" target="_blank" rel="nofollow">7,668,948</a></td>
<td valign="top">Staggered time zones</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,945" target="_blank" rel="nofollow">7,668,945</a></td>
<td valign="top">Network booting using a platform management coprocessor</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,698" target="_blank" rel="nofollow">7,668,698</a></td>
<td valign="top">Duty cycle calibration for receiver clock</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,614" target="_blank" rel="nofollow">7,668,614</a></td>
<td valign="top">Optimization-based process scheduling method and system</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,524" target="_blank" rel="nofollow">7,668,524</a></td>
<td valign="top">Clock deskewing method, apparatus, and system</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,387" target="_blank" rel="nofollow">7,668,387</a></td>
<td valign="top">Selective local transient improvement and peaking for video sharpness enhancement</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,306" target="_blank" rel="nofollow">7,668,306</a></td>
<td valign="top">Method and apparatus for connecting packet telephony calls between secure and non-secure networks</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,260" target="_blank" rel="nofollow">7,668,260</a></td>
<td valign="top">Method of and apparatus for detecting impulsive noise, method of operating a demodulator, demodulator and radio receiver</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,194" target="_blank" rel="nofollow">7,668,194</a></td>
<td valign="top">Dual speed interface between media access control unit and physical unit</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,165" target="_blank" rel="nofollow">7,668,165</a></td>
<td valign="top">Hardware-based multi-threading for packet processing</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,160" target="_blank" rel="nofollow">7,668,160</a></td>
<td valign="top">Methods for performing packet classification</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,147" target="_blank" rel="nofollow">7,668,147</a></td>
<td valign="top">Communication system with fast control traffic</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,139" target="_blank" rel="nofollow">7,668,139</a></td>
<td valign="top">Mobile handover utilizing multicast in a multi-protocol label switching (MPLS)-based network</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,129" target="_blank" rel="nofollow">7,668,129</a></td>
<td valign="top">Learning mechanism to configure power save parameters for automatic power save delivery</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,121" target="_blank" rel="nofollow">7,668,121</a></td>
<td valign="top">Purging of authentication key contexts by base stations on handoff</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,102" target="_blank" rel="nofollow">7,668,102</a></td>
<td valign="top">Techniques to manage retransmissions in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,098" target="_blank" rel="nofollow">7,668,098</a></td>
<td valign="top">Method and apparatus for improving the upstream data transfer rate for a cable modem</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,507" target="_blank" rel="nofollow">7,667,507</a></td>
<td valign="top">Edge-timing adjustment circuit</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,447" target="_blank" rel="nofollow">7,667,447</a></td>
<td valign="top">Load adaptive power delivery</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,320" target="_blank" rel="nofollow">7,667,320</a></td>
<td valign="top">Integrated circuit package with improved power signal connection</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,319" target="_blank" rel="nofollow">7,667,319</a></td>
<td valign="top">Electroosmotic pump using nanoporous dielectric frit</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,796" target="_blank" rel="nofollow">7,666,796</a></td>
<td valign="top">Substrate patterning for multi-gate transistors</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,778" target="_blank" rel="nofollow">7,666,778</a></td>
<td valign="top">Method of arranging solder balls for ball grid array packages</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,768" target="_blank" rel="nofollow">7,666,768</a></td>
<td valign="top">Through-die metal vias with a dispersed phase of graphitic structures of carbon for reduced thermal expansion and increased electrical conductance</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,727" target="_blank" rel="nofollow">7,666,727</a></td>
<td valign="top">Semiconductor device having a laterally modulated gate workfunction and method of fabrication</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,714" target="_blank" rel="nofollow">7,666,714</a></td>
<td valign="top">Assembly of thin die coreless package</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,555" target="_blank" rel="nofollow">7,666,555</a></td>
<td valign="top">Pellicle, methods of fabrication and methods of use for extreme ultraviolet lithography</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,465" target="_blank" rel="nofollow">7,666,465</a></td>
<td valign="top">Introducing nanotubes in trenches and structures formed thereby</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,665,399" target="_blank" rel="nofollow">7,665,399</a></td>
<td valign="top">System and method for vacuum generated imprinting</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Intel patent applications published on 18 February 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-18-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-18-february-2010/#comments</comments>
		<pubDate>Thu, 18 Feb 2010 13:35:49 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8102</guid>
		<description><![CDATA[1 US patent application published on 18 February 2010 and assigned to Intel



1
20100042579
GENERATING AND/OR RECEIVING, AT LEAST IN PART, AT LEAST ONE DATA ACCESS REQUEST


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 18 February 2010 and assigned to Intel<br />
<span id="more-8102"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100042579.PGNR.&#038;OS=DN/20100042579RS=DN/20100042579" target="_blank">20100042579</a></td>
<td valign="top">GENERATING AND/OR RECEIVING, AT LEAST IN PART, AT LEAST ONE DATA ACCESS REQUEST</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Intel patents granted on 16 February 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-16-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-16-february-2010/#comments</comments>
		<pubDate>Tue, 16 Feb 2010 15:09:04 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8065</guid>
		<description><![CDATA[23 US patents granted on 16 February 2010 and assigned to Intel



1
7,665,008
Method and apparatus for implementing a low density parity check code in a wireless system


2
7,665,005
In situ processor margin testing


3
7,665,000
Meeting point thread characterization


4
7,664,970
Method and apparatus for a zero voltage processor sleep state


5
7,664,915
High performance raid-6 system architecture with pattern matching


6
7,664,892
Method, system, and program for managing data [...]]]></description>
			<content:encoded><![CDATA[<p>23 US patents granted on 16 February 2010 and assigned to Intel<br />
<span id="more-8065"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,665,008" target="_blank" rel="nofollow">7,665,008</a></td>
<td valign="top">Method and apparatus for implementing a low density parity check code in a wireless system</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,665,005" target="_blank" rel="nofollow">7,665,005</a></td>
<td valign="top">In situ processor margin testing</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,665,000" target="_blank" rel="nofollow">7,665,000</a></td>
<td valign="top">Meeting point thread characterization</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,970" target="_blank" rel="nofollow">7,664,970</a></td>
<td valign="top">Method and apparatus for a zero voltage processor sleep state</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,915" target="_blank" rel="nofollow">7,664,915</a></td>
<td valign="top">High performance raid-6 system architecture with pattern matching</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,892" target="_blank" rel="nofollow">7,664,892</a></td>
<td valign="top">Method, system, and program for managing data read operations on network controller with offloading functions</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,889" target="_blank" rel="nofollow">7,664,889</a></td>
<td valign="top">DMA descriptor management mechanism</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,648" target="_blank" rel="nofollow">7,664,648</a></td>
<td valign="top">Method and apparatus to provision a network appliance</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,529" target="_blank" rel="nofollow">7,664,529</a></td>
<td valign="top">Methods and apparatus for data communication for mobile electronic devices</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,274" target="_blank" rel="nofollow">7,664,274</a></td>
<td valign="top">Enhanced acoustic transmission system and method</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,269" target="_blank" rel="nofollow">7,664,269</a></td>
<td valign="top">Encrypting message for secure transmission</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,215" target="_blank" rel="nofollow">7,664,215</a></td>
<td valign="top">Signal alignment based on data signal</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,119" target="_blank" rel="nofollow">7,664,119</a></td>
<td valign="top">Method and apparatus to perform network routing</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,085" target="_blank" rel="nofollow">7,664,085</a></td>
<td valign="top">Wireless communication device and method for coordinating communications among wireless local area networks (WLANs) and broadband wireless access (BWA) networks</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,037" target="_blank" rel="nofollow">7,664,037</a></td>
<td valign="top">Multichannel mesh network, multichannel mesh router and methods for routing using bottleneck channel identifiers</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,490" target="_blank" rel="nofollow">7,663,490</a></td>
<td valign="top">Methods and apparatus for efficiently tracking activity using radio frequency identification</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,442" target="_blank" rel="nofollow">7,663,442</a></td>
<td valign="top">Data receiver including a transconductance amplifier</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,230" target="_blank" rel="nofollow">7,663,230</a></td>
<td valign="top">Methods of forming channels on an integrated circuit die and die cooling systems including such channels</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,192" target="_blank" rel="nofollow">7,663,192</a></td>
<td valign="top">CMOS device and method of manufacturing same</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,172" target="_blank" rel="nofollow">7,663,172</a></td>
<td valign="top">Vertical memory device and method</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,689" target="_blank" rel="nofollow">7,662,689</a></td>
<td valign="top">Strained transistor integration for CMOS</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,674" target="_blank" rel="nofollow">7,662,674</a></td>
<td valign="top">Methods of forming electromigration and thermal gradient based fuse structures</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,501" target="_blank" rel="nofollow">7,662,501</a></td>
<td valign="top">Transpiration cooling and fuel cell for ultra mobile applications</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 11 February 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-11-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-11-february-2010/#comments</comments>
		<pubDate>Thu, 11 Feb 2010 14:16:46 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8026</guid>
		<description><![CDATA[No US patent applications published on 11 February 2010 and assigned to Intel
]]></description>
			<content:encoded><![CDATA[<p>No US patent applications published on 11 February 2010 and assigned to Intel</p>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 09 February 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-09-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-09-february-2010/#comments</comments>
		<pubDate>Tue, 09 Feb 2010 14:38:05 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7987</guid>
		<description><![CDATA[20 US patents granted on 09 February 2010 and assigned to Intel



1
7,661,054
Methods and arrangements to remap degraded storage blocks


2
7,661,038
Link adaptation for retransmission error-control technique transmissions


3
7,660,977
System and method to control microcode updates after booting an operating system in a computing platform


4
7,660,922
Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports


5
7,660,913
Out-of-band platform recovery


6
7,660,371
Normalized auto-correlators


7
7,660,349
Transmit equalizer [...]]]></description>
			<content:encoded><![CDATA[<p>20 US patents granted on 09 February 2010 and assigned to Intel<br />
<span id="more-7987"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,661,054" target="_blank" rel="nofollow">7,661,054</a></td>
<td valign="top">Methods and arrangements to remap degraded storage blocks</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,661,038" target="_blank" rel="nofollow">7,661,038</a></td>
<td valign="top">Link adaptation for retransmission error-control technique transmissions</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,977" target="_blank" rel="nofollow">7,660,977</a></td>
<td valign="top">System and method to control microcode updates after booting an operating system in a computing platform</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,922" target="_blank" rel="nofollow">7,660,922</a></td>
<td valign="top">Mechanism to flexibly support multiple device numbers on point-to-point interconnect upstream ports</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,913" target="_blank" rel="nofollow">7,660,913</a></td>
<td valign="top">Out-of-band platform recovery</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,371" target="_blank" rel="nofollow">7,660,371</a></td>
<td valign="top">Normalized auto-correlators</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,349" target="_blank" rel="nofollow">7,660,349</a></td>
<td valign="top">Transmit equalizer compensation for probe receivers</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,298" target="_blank" rel="nofollow">7,660,298</a></td>
<td valign="top">Systems and techniques for optimistic caching for address translations</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,289" target="_blank" rel="nofollow">7,660,289</a></td>
<td valign="top">System, apparatus and method of varying channel bandwidth</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,278" target="_blank" rel="nofollow">7,660,278</a></td>
<td valign="top">Methods and apparatus for providing a roaming support system</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,276" target="_blank" rel="nofollow">7,660,276</a></td>
<td valign="top">System and related methods for beamforming in a multi-point communications environment</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,268" target="_blank" rel="nofollow">7,660,268</a></td>
<td valign="top">Determining the presence of IP multicast routers</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,054" target="_blank" rel="nofollow">7,660,054</a></td>
<td valign="top">Thermally controlled sold immersion lens fixture</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,977" target="_blank" rel="nofollow">7,659,977</a></td>
<td valign="top">Apparatus and method for imaging with surface enhanced coherent anti-stokes raman scattering (SECARS)</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,762" target="_blank" rel="nofollow">7,659,762</a></td>
<td valign="top">Clock synchronizer</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,753" target="_blank" rel="nofollow">7,659,753</a></td>
<td valign="top">Analog comparator with precise threshold control</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,196" target="_blank" rel="nofollow">7,659,196</a></td>
<td valign="top">Soluble hard mask for interlayer dielectric patterning</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,192" target="_blank" rel="nofollow">7,659,192</a></td>
<td valign="top">Methods of forming stepped bumps and structures formed thereby</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,143" target="_blank" rel="nofollow">7,659,143</a></td>
<td valign="top">Dual-chip integrated heat spreader assembly, packages containing same, and systems containing same</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,658,975" target="_blank" rel="nofollow">7,658,975</a></td>
<td valign="top">Sealing porous dielectric materials</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 04 February 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-04-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-04-february-2010/#comments</comments>
		<pubDate>Thu, 04 Feb 2010 19:28:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7947</guid>
		<description><![CDATA[1 US patent application published on 04 February 2010 and assigned to Intel



1
20100030930
BANDWIDTH CONSERVING PROTOCOL FOR COMMAND-RESPONSE BUS SYSTEM


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 04 February 2010 and assigned to Intel<br />
<span id="more-7947"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100030930.PGNR.&#038;OS=DN/20100030930RS=DN/20100030930" target="_blank">20100030930</a></td>
<td valign="top">BANDWIDTH CONSERVING PROTOCOL FOR COMMAND-RESPONSE BUS SYSTEM</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patents granted on 02 February 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-02-february-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-02-february-2010/#comments</comments>
		<pubDate>Tue, 02 Feb 2010 14:01:23 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7906</guid>
		<description><![CDATA[34 US patents granted on 02 February 2010 and assigned to Intel



1
7,657,894
Detecting lock acquisition hierarchy violations in multithreaded programs


2
7,657,881
Using optimized libraries to improve performance of deployed application code at runtime


3
7,657,880
Safe store for speculative helper threads


4
7,657,862
Synchronous elastic designs with early evaluation


5
7,657,767
Cache leakage shut-off mechanism


6
7,657,766
Apparatus for an energy efficient clustered micro-architecture


7
7,657,724
Addressing device resources in variable page size [...]]]></description>
			<content:encoded><![CDATA[<p>34 US patents granted on 02 February 2010 and assigned to Intel<br />
<span id="more-7906"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,894" target="_blank" rel="nofollow">7,657,894</a></td>
<td valign="top">Detecting lock acquisition hierarchy violations in multithreaded programs</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,881" target="_blank" rel="nofollow">7,657,881</a></td>
<td valign="top">Using optimized libraries to improve performance of deployed application code at runtime</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,880" target="_blank" rel="nofollow">7,657,880</a></td>
<td valign="top">Safe store for speculative helper threads</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,862" target="_blank" rel="nofollow">7,657,862</a></td>
<td valign="top">Synchronous elastic designs with early evaluation</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,767" target="_blank" rel="nofollow">7,657,767</a></td>
<td valign="top">Cache leakage shut-off mechanism</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,766" target="_blank" rel="nofollow">7,657,766</a></td>
<td valign="top">Apparatus for an energy efficient clustered micro-architecture</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,724" target="_blank" rel="nofollow">7,657,724</a></td>
<td valign="top">Addressing device resources in variable page size environments</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,698" target="_blank" rel="nofollow">7,657,698</a></td>
<td valign="top">Systems and methods for chassis identification</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,693" target="_blank" rel="nofollow">7,657,693</a></td>
<td valign="top">Router to use three levels of arbitration for a crossbar channel</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,232" target="_blank" rel="nofollow">7,657,232</a></td>
<td valign="top">Offset-frequency loop-back calibration</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,228" target="_blank" rel="nofollow">7,657,228</a></td>
<td valign="top">Device, system and method of noise identification and cancellation</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,131" target="_blank" rel="nofollow">7,657,131</a></td>
<td valign="top">Systems and methods for integrated optical circuitry for high data rate optical transmission and reception</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,079" target="_blank" rel="nofollow">7,657,079</a></td>
<td valign="top">Single constraint at a time (SCAAT) tracking of a virtual reality (VR) display</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,983" target="_blank" rel="nofollow">7,656,983</a></td>
<td valign="top">Dual clock domain deskew circuit</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,892" target="_blank" rel="nofollow">7,656,892</a></td>
<td valign="top">Method and apparatus of multi-entity wireless communication adapter</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,891" target="_blank" rel="nofollow">7,656,891</a></td>
<td valign="top">Method and apparatus enabling concurrent processing of contiguously and virtually concatenated payloads</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,707" target="_blank" rel="nofollow">7,656,707</a></td>
<td valign="top">Systems and methods for discrete channel decoding of LDPC codes for flash memory</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,702" target="_blank" rel="nofollow">7,656,702</a></td>
<td valign="top">Ultra low voltage, low leakage, high density, variation tolerant memory bit cells</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,682" target="_blank" rel="nofollow">7,656,682</a></td>
<td valign="top">Electromagnetic noise reduction device</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,644" target="_blank" rel="nofollow">7,656,644</a></td>
<td valign="top">iTFC with optimized C(T)</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,635" target="_blank" rel="nofollow">7,656,635</a></td>
<td valign="top">Overheat detection in thermally controlled devices</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,523" target="_blank" rel="nofollow">7,656,523</a></td>
<td valign="top">Multiplexed raman detection with filter set</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,410" target="_blank" rel="nofollow">7,656,410</a></td>
<td valign="top">Image buffering techniques</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,409" target="_blank" rel="nofollow">7,656,409</a></td>
<td valign="top">Graphics processing on a processor core</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,397" target="_blank" rel="nofollow">7,656,397</a></td>
<td valign="top">Pointing device with integrated audio input and associated methods</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,387" target="_blank" rel="nofollow">7,656,387</a></td>
<td valign="top">Method and machine-accessible medium for controlling multiple processing units with a single input device</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,226" target="_blank" rel="nofollow">7,656,226</a></td>
<td valign="top">Switched capacitor equalizer with offset voltage cancelling</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,200" target="_blank" rel="nofollow">7,656,200</a></td>
<td valign="top">Multiple-phase, differential sampling and steering</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,184" target="_blank" rel="nofollow">7,656,184</a></td>
<td valign="top">Detecting counterfeit products</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,151" target="_blank" rel="nofollow">7,656,151</a></td>
<td valign="top">Printed circuit board with an opening to access components attached to the printed circuit board</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,035" target="_blank" rel="nofollow">7,656,035</a></td>
<td valign="top">C4 joint reliability</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,986" target="_blank" rel="nofollow">7,655,986</a></td>
<td valign="top">Systems and methods for reducing contact to gate shorts</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,517" target="_blank" rel="nofollow">7,655,517</a></td>
<td valign="top">Spin polarization amplifying transistor</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,654,433" target="_blank" rel="nofollow">7,654,433</a></td>
<td valign="top">Flux overspray removal masks with channels, methods of assembling same, and systems containing same</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 28 January 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-28-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-28-january-2010/#comments</comments>
		<pubDate>Thu, 28 Jan 2010 13:19:42 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7866</guid>
		<description><![CDATA[3 US patent applications published on 28 January 2010 and assigned to Intel



1
20100023782
CRYPTOGRAPHIC KEY-TO-POLICY ASSOCIATION AND ENFORCEMENT FOR SECURE KEY-MANAGEMENT AND POLICY EXECUTION


2
20100023768
Method and system for security key agreement


3
20100022083
CARBON NANOTUBE INTERCONNECT STRUCTURES


]]></description>
			<content:encoded><![CDATA[<p>3 US patent applications published on 28 January 2010 and assigned to Intel<br />
<span id="more-7866"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100023782.PGNR.&#038;OS=DN/20100023782RS=DN/20100023782" target="_blank">20100023782</a></td>
<td valign="top">CRYPTOGRAPHIC KEY-TO-POLICY ASSOCIATION AND ENFORCEMENT FOR SECURE KEY-MANAGEMENT AND POLICY EXECUTION</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100023768.PGNR.&#038;OS=DN/20100023768RS=DN/20100023768" target="_blank">20100023768</a></td>
<td valign="top">Method and system for security key agreement</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100022083.PGNR.&#038;OS=DN/20100022083RS=DN/20100022083" target="_blank">20100022083</a></td>
<td valign="top">CARBON NANOTUBE INTERCONNECT STRUCTURES</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patents granted on 26 January 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-26-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-26-january-2010/#comments</comments>
		<pubDate>Tue, 26 Jan 2010 15:51:23 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7825</guid>
		<description><![CDATA[35 US patents granted on 26 January 2010 and assigned to Intel



1
7,653,929
Power management apparatus, systems, and methods


2
7,653,906
Apparatus and method for reducing power consumption on simultaneous multi-threading systems


3
7,653,904
System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected


4
7,653,864
Method and apparatus to perform [...]]]></description>
			<content:encoded><![CDATA[<p>35 US patents granted on 26 January 2010 and assigned to Intel<br />
<span id="more-7825"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,929" target="_blank" rel="nofollow">7,653,929</a></td>
<td valign="top">Power management apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,906" target="_blank" rel="nofollow">7,653,906</a></td>
<td valign="top">Apparatus and method for reducing power consumption on simultaneous multi-threading systems</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,904" target="_blank" rel="nofollow">7,653,904</a></td>
<td valign="top">System for forming a critical update loop to continuously reload active thread state from a register storing thread state until another active thread is detected</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,864" target="_blank" rel="nofollow">7,653,864</a></td>
<td valign="top">Method and apparatus to perform error control</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,850" target="_blank" rel="nofollow">7,653,850</a></td>
<td valign="top">Delay fault detection using latch with error sampling</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,846" target="_blank" rel="nofollow">7,653,846</a></td>
<td valign="top">Memory cell bit valve loss detection and restoration</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,808" target="_blank" rel="nofollow">7,653,808</a></td>
<td valign="top">Providing selectable processor abstraction layer components within one BIOS program</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,786" target="_blank" rel="nofollow">7,653,786</a></td>
<td valign="top">Power reduction for processor front-end by caching decoded instructions</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,727" target="_blank" rel="nofollow">7,653,727</a></td>
<td valign="top">Cooperative embedded agents</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,392" target="_blank" rel="nofollow">7,653,392</a></td>
<td valign="top">Methods and systems for heterogeneous wireless network discovery and selection</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,368" target="_blank" rel="nofollow">7,653,368</a></td>
<td valign="top">Radio receiver and a method thereof</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,367" target="_blank" rel="nofollow">7,653,367</a></td>
<td valign="top">Squelch detector</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,257" target="_blank" rel="nofollow">7,653,257</a></td>
<td valign="top">Enhancing video sequence sharpness by adaptive peaking</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,196" target="_blank" rel="nofollow">7,653,196</a></td>
<td valign="top">Apparatus and method for performing RC4 ciphering</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,167" target="_blank" rel="nofollow">7,653,167</a></td>
<td valign="top">Phase deglitch circuit for phase interpolator for high-speed serial I/O applications</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,165" target="_blank" rel="nofollow">7,653,165</a></td>
<td valign="top">Pulse amplitude modulated system with reduced intersymbol interference</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,164" target="_blank" rel="nofollow">7,653,164</a></td>
<td valign="top">Adaptive IQ imbalance correction for multicarrier wireless communication systems</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,163" target="_blank" rel="nofollow">7,653,163</a></td>
<td valign="top">Systems for communicating using multiple frequency bands in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,147" target="_blank" rel="nofollow">7,653,147</a></td>
<td valign="top">Transmitter control</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,119" target="_blank" rel="nofollow">7,653,119</a></td>
<td valign="top">Extending orthogonal frequency division multiplexed wireless local area networks using direct sequence spread spectrum/complementary code keying</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,069" target="_blank" rel="nofollow">7,653,069</a></td>
<td valign="top">Two stage queue arbitration</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,035" target="_blank" rel="nofollow">7,653,035</a></td>
<td valign="top">Interference rejection in wireless receivers</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,032" target="_blank" rel="nofollow">7,653,032</a></td>
<td valign="top">Applying wireless network connection profiles using windows management instrumentation</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,653,014" target="_blank" rel="nofollow">7,653,014</a></td>
<td valign="top">Configuring a transmission mode between devices</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,910" target="_blank" rel="nofollow">7,652,910</a></td>
<td valign="top">Floating body memory array</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,882" target="_blank" rel="nofollow">7,652,882</a></td>
<td valign="top">Method and apparatus for dissipating heat from an electronic device</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,624" target="_blank" rel="nofollow">7,652,624</a></td>
<td valign="top">Millimeter-wave communication stations with directional antennas and methods for fast link recovery</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,459" target="_blank" rel="nofollow">7,652,459</a></td>
<td valign="top">Adaptive controller with mode tracking and parametric estimation for digital power converters</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,373" target="_blank" rel="nofollow">7,652,373</a></td>
<td valign="top">Power delivery using an integrated heat spreader</td>
</tr>
<tr>
<td valign="top" align="right">30</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,372" target="_blank" rel="nofollow">7,652,372</a></td>
<td valign="top">Microfluidic cooling of integrated circuits</td>
</tr>
<tr>
<td valign="top" align="right">31</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,272" target="_blank" rel="nofollow">7,652,272</a></td>
<td valign="top">Plasma-based debris mitigation for extreme ultraviolet (EUV) light source</td>
</tr>
<tr>
<td valign="top" align="right">32</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,308" target="_blank" rel="nofollow">7,651,308</a></td>
<td valign="top">Carrier to hold semiconductor device using opposed rollers</td>
</tr>
<tr>
<td valign="top" align="right">33</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,021" target="_blank" rel="nofollow">7,651,021</a></td>
<td valign="top">Microball attachment using self-assembly for substrate bumping</td>
</tr>
<tr>
<td valign="top" align="right">34</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,020" target="_blank" rel="nofollow">7,651,020</a></td>
<td valign="top">Amphiphilic block copolymers for improved flux application</td>
</tr>
<tr>
<td valign="top" align="right">35</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,694" target="_blank" rel="nofollow">7,650,694</a></td>
<td valign="top">Method for forming multilayer substrate</td>
</tr>
</table>
]]></content:encoded>
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		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Intel patent applications published on 21 January 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-21-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-21-january-2010/#comments</comments>
		<pubDate>Thu, 21 Jan 2010 16:25:21 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7791</guid>
		<description><![CDATA[2 US patent applications published on 21 January 2010 and assigned to Intel



1
20100017549
MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS


2
20100011872
METHOD AND APPARATUS FOR A SELF-POWERED RFID-READABLE PEDOMETER


]]></description>
			<content:encoded><![CDATA[<p>2 US patent applications published on 21 January 2010 and assigned to Intel<br />
<span id="more-7791"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100017549.PGNR.&#038;OS=DN/20100017549RS=DN/20100017549" target="_blank">20100017549</a></td>
<td valign="top">MECHANISM TO FLEXIBLY SUPPORT MULTIPLE DEVICE NUMBERS ON POINT-TO-POINT INTERCONNECT UPSTREAM PORTS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100011872.PGNR.&#038;OS=DN/20100011872RS=DN/20100011872" target="_blank">20100011872</a></td>
<td valign="top">METHOD AND APPARATUS FOR A SELF-POWERED RFID-READABLE PEDOMETER</td>
</tr>
</table>
]]></content:encoded>
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		<title>Intel patents granted on 19 January 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-19-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-19-january-2010/#comments</comments>
		<pubDate>Tue, 19 Jan 2010 15:33:29 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7768</guid>
		<description><![CDATA[29 US patents granted on 19 January 2010 and assigned to Intel



1
7,650,558
Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems


2
7,650,540
Detecting and differentiating SATA loopback modes


3
7,650,518
Method, apparatus, and system for increasing single core performance in a multi-core microprocessor


4
7,650,489
Determining coherency between a non-volatile memory and a system


5
7,650,488
Communication [...]]]></description>
			<content:encoded><![CDATA[<p>29 US patents granted on 19 January 2010 and assigned to Intel<br />
<span id="more-7768"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,558" target="_blank" rel="nofollow">7,650,558</a></td>
<td valign="top">Systems, methods, and apparatuses for using the same memory type for both error check and non-error check memory systems</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,540" target="_blank" rel="nofollow">7,650,540</a></td>
<td valign="top">Detecting and differentiating SATA loopback modes</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,518" target="_blank" rel="nofollow">7,650,518</a></td>
<td valign="top">Method, apparatus, and system for increasing single core performance in a multi-core microprocessor</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,489" target="_blank" rel="nofollow">7,650,489</a></td>
<td valign="top">Determining coherency between a non-volatile memory and a system</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,488" target="_blank" rel="nofollow">7,650,488</a></td>
<td valign="top">Communication between processor core partitions with exclusive read or write to descriptor queues for shared memory space</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,464" target="_blank" rel="nofollow">7,650,464</a></td>
<td valign="top">Object relocation guided by data cache miss profile</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,459" target="_blank" rel="nofollow">7,650,459</a></td>
<td valign="top">High speed interface for non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,372" target="_blank" rel="nofollow">7,650,372</a></td>
<td valign="top">Method and apparatus for varying-radix numeration system</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,273" target="_blank" rel="nofollow">7,650,273</a></td>
<td valign="top">Performance simulation of multiprocessor systems</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,271" target="_blank" rel="nofollow">7,650,271</a></td>
<td valign="top">Time-domain device noise simulator</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,117" target="_blank" rel="nofollow">7,650,117</a></td>
<td valign="top">Mitigating interference between wireless systems</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,955" target="_blank" rel="nofollow">7,649,955</a></td>
<td valign="top">MIMO receiver and method for beamforming using CORDIC operations</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,868" target="_blank" rel="nofollow">7,649,868</a></td>
<td valign="top">Method and system for evaluating a wireless link</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,861" target="_blank" rel="nofollow">7,649,861</a></td>
<td valign="top">Multiple antenna multicarrier communication system and method with reduced mobile-station processing</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,845" target="_blank" rel="nofollow">7,649,845</a></td>
<td valign="top">Handling hot spots in interconnection networks</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,836" target="_blank" rel="nofollow">7,649,836</a></td>
<td valign="top">Link state machine for the advanced switching (AS) architecture</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,833" target="_blank" rel="nofollow">7,649,833</a></td>
<td valign="top">Multichannel orthogonal frequency division multiplexed receivers with antenna selection and maximum-ratio combining and associated methods</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,745" target="_blank" rel="nofollow">7,649,745</a></td>
<td valign="top">Circuit board including stubless signal paths and method of making same</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,429" target="_blank" rel="nofollow">7,649,429</a></td>
<td valign="top">Controlling coupling strength in electromagnetic bus coupling</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,407" target="_blank" rel="nofollow">7,649,407</a></td>
<td valign="top">Digitally tuned, integrated RF filters with enhanced linearity for multi-band radio applications</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,396" target="_blank" rel="nofollow">7,649,396</a></td>
<td valign="top">Soft error rate hardened latch</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,388" target="_blank" rel="nofollow">7,649,388</a></td>
<td valign="top">Analog voltage recovery circuit</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,385" target="_blank" rel="nofollow">7,649,385</a></td>
<td valign="top">Logic with state retentive sleep mode</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,371" target="_blank" rel="nofollow">7,649,371</a></td>
<td valign="top">Thermal stratification methods</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,265" target="_blank" rel="nofollow">7,649,265</a></td>
<td valign="top">Micro-via structure design for high performance integrated circuits</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,264" target="_blank" rel="nofollow">7,649,264</a></td>
<td valign="top">Hard mask for low-k interlayer dielectric patterning</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,239" target="_blank" rel="nofollow">7,649,239</a></td>
<td valign="top">Dielectric spacers for metal interconnects and method to form the same</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,191" target="_blank" rel="nofollow">7,649,191</a></td>
<td valign="top">Forming a carbon layer between phase change layers of a phase change memory</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,803" target="_blank" rel="nofollow">7,648,803</a></td>
<td valign="top">Diagonal corner-to-corner sub-resolution assist features for photolithography</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patent applications published on 14 January 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-14-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patent-applications-published-on-14-january-2010/#comments</comments>
		<pubDate>Thu, 14 Jan 2010 14:04:14 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/intel-patent-applications-published-on-14-january-2010/</guid>
		<description><![CDATA[1 US patent application published on 14 January 2010 and assigned to Intel



1
20100008408
GERAN TRANSCEIVER AND METHOD FOR COOPERATIVE CHANNEL ENCODING ACROSS MULTIPLE GERAN TONAL CARRIERS


]]></description>
			<content:encoded><![CDATA[<p>1 US patent application published on 14 January 2010 and assigned to Intel<br />
<span id="more-7747"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100008408.PGNR.&#038;OS=DN/20100008408RS=DN/20100008408" target="_blank">20100008408</a></td>
<td valign="top">GERAN TRANSCEIVER AND METHOD FOR COOPERATIVE CHANNEL ENCODING ACROSS MULTIPLE GERAN TONAL CARRIERS</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Intel patents granted on 12 January 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-12-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-12-january-2010/#comments</comments>
		<pubDate>Tue, 12 Jan 2010 16:03:09 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7724</guid>
		<description><![CDATA[21 US patents granted on 12 January 2010 and assigned to Intel



1
7,647,616
Method to measure the perceived quality of streaming media


2
7,647,585
Methods and apparatus to detect patterns in programs


3
7,647,557
Techniques for shuffling video information


4
7,647,536
Repair bits for a low voltage cache


5
7,647,509
Method and apparatus for managing power in a processing system with multiple partitions


6
7,647,508
Methods and apparatus for providing integrity protection [...]]]></description>
			<content:encoded><![CDATA[<p>21 US patents granted on 12 January 2010 and assigned to Intel<br />
<span id="more-7724"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,616" target="_blank" rel="nofollow">7,647,616</a></td>
<td valign="top">Method to measure the perceived quality of streaming media</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,585" target="_blank" rel="nofollow">7,647,585</a></td>
<td valign="top">Methods and apparatus to detect patterns in programs</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,557" target="_blank" rel="nofollow">7,647,557</a></td>
<td valign="top">Techniques for shuffling video information</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,536" target="_blank" rel="nofollow">7,647,536</a></td>
<td valign="top">Repair bits for a low voltage cache</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,509" target="_blank" rel="nofollow">7,647,509</a></td>
<td valign="top">Method and apparatus for managing power in a processing system with multiple partitions</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,508" target="_blank" rel="nofollow">7,647,508</a></td>
<td valign="top">Methods and apparatus for providing integrity protection for management and control traffic of wireless communication networks</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,482" target="_blank" rel="nofollow">7,647,482</a></td>
<td valign="top">Methods and apparatus for dynamic register scratching</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,476" target="_blank" rel="nofollow">7,647,476</a></td>
<td valign="top">Common analog interface for multiple processor cores</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,474" target="_blank" rel="nofollow">7,647,474</a></td>
<td valign="top">Saving system context in the event of power loss</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,868" target="_blank" rel="nofollow">7,646,868</a></td>
<td valign="top">Method for steganographic cryptography</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,779" target="_blank" rel="nofollow">7,646,779</a></td>
<td valign="top">Hierarchical packet scheduler using hole-filling and multiple packet buffering</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,759" target="_blank" rel="nofollow">7,646,759</a></td>
<td valign="top">Apparatus and method for configuring data plane behavior on network forwarding elements</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,716" target="_blank" rel="nofollow">7,646,716</a></td>
<td valign="top">Packet processing in a wireless network</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,701" target="_blank" rel="nofollow">7,646,701</a></td>
<td valign="top">Incremental redundancy using high-order modulation and coding schemes</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,607" target="_blank" rel="nofollow">7,646,607</a></td>
<td valign="top">Quasi-radial heatsink with rectangular form factor and uniform fin length</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,214" target="_blank" rel="nofollow">7,646,214</a></td>
<td valign="top">Power harvesting signal line termination</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,108" target="_blank" rel="nofollow">7,646,108</a></td>
<td valign="top">Multiple output voltage regulator</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,093" target="_blank" rel="nofollow">7,646,093</a></td>
<td valign="top">Thermal management of dies on a secondary side of a package</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,071" target="_blank" rel="nofollow">7,646,071</a></td>
<td valign="top">Asymmetric channel doping for improved memory operation for floating body cell (FBC) memory</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,645,368" target="_blank" rel="nofollow">7,645,368</a></td>
<td valign="top">Orientation independent electroosmotic pump</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,871" target="_blank" rel="nofollow">7,644,871</a></td>
<td valign="top">Flux spray atomization and splash control</td>
</tr>
</table>
]]></content:encoded>
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		<title>Intel patent applications published on 07 January 2010</title>
		<link>http://www.latestpatents.com/intel-patent-applications-published-on-07-january-2010/</link>
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		<pubDate>Thu, 07 Jan 2010 14:36:33 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patent Applications]]></category>

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		<description><![CDATA[No US patent applications published on 07 January 2010 and assigned to Intel
]]></description>
			<content:encoded><![CDATA[<p>No US patent applications published on 07 January 2010 and assigned to Intel</p>
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		<title>Intel patents granted on 05 January 2010</title>
		<link>http://www.latestpatents.com/intel-patents-granted-on-05-january-2010/</link>
		<comments>http://www.latestpatents.com/intel-patents-granted-on-05-january-2010/#comments</comments>
		<pubDate>Tue, 05 Jan 2010 14:37:12 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Intel]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7679</guid>
		<description><![CDATA[29 US patents granted on 05 January 2010 and assigned to Intel



1
7,644,407
Method, apparatus and system for seamlessly sharing a graphics device amongst virtual machines


2
7,644,347
Silent data corruption mitigation using error correction code with embedded signaling fault detection


3
7,644,345
Bit distributor for multicarrier communication systems employing adaptive bit loading for multiple spatial streams and methods


4
7,644,344
Latency by offsetting cyclic redundancy [...]]]></description>
			<content:encoded><![CDATA[<p>29 US patents granted on 05 January 2010 and assigned to Intel<br />
<span id="more-7679"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,407" target="_blank" rel="nofollow">7,644,407</a></td>
<td valign="top">Method, apparatus and system for seamlessly sharing a graphics device amongst virtual machines</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,347" target="_blank" rel="nofollow">7,644,347</a></td>
<td valign="top">Silent data corruption mitigation using error correction code with embedded signaling fault detection</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,345" target="_blank" rel="nofollow">7,644,345</a></td>
<td valign="top">Bit distributor for multicarrier communication systems employing adaptive bit loading for multiple spatial streams and methods</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,344" target="_blank" rel="nofollow">7,644,344</a></td>
<td valign="top">Latency by offsetting cyclic redundancy code lanes from data lanes</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,328" target="_blank" rel="nofollow">7,644,328</a></td>
<td valign="top">Sharing routing of a test signal with an alternative power supply to combinatorial logic for low power design</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,293" target="_blank" rel="nofollow">7,644,293</a></td>
<td valign="top">Method and apparatus for dynamically controlling power management in a distributed system</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,250" target="_blank" rel="nofollow">7,644,250</a></td>
<td valign="top">Defining pin functionality at device power on</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,248" target="_blank" rel="nofollow">7,644,248</a></td>
<td valign="top">Mechanism to generate logically dedicated read and write channels in a memory controller</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,236" target="_blank" rel="nofollow">7,644,236</a></td>
<td valign="top">Memory cache bank prediction</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,225" target="_blank" rel="nofollow">7,644,225</a></td>
<td valign="top">Performance or power-optimized code/data storage for nonvolatile memories</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,188" target="_blank" rel="nofollow">7,644,188</a></td>
<td valign="top">Distributing tasks in data communications</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,142" target="_blank" rel="nofollow">7,644,142</a></td>
<td valign="top">Methods and apparatus to perform process placement for distributed applications</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,130" target="_blank" rel="nofollow">7,644,130</a></td>
<td valign="top">Method and apparatus for transparent selection of alternate network interfaces in a message passing interface (&#8221;MPI&#8221;) implementation</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,049" target="_blank" rel="nofollow">7,644,049</a></td>
<td valign="top">Decision forest based classifier for determining predictive importance in real-time data analysis</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,803" target="_blank" rel="nofollow">7,643,803</a></td>
<td valign="top">Power estimation of a transmission</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,710" target="_blank" rel="nofollow">7,643,710</a></td>
<td valign="top">Method and apparatus for efficient coupling between silicon photonic chip and optical fiber</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,551" target="_blank" rel="nofollow">7,643,551</a></td>
<td valign="top">Compressing video frames</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,519" target="_blank" rel="nofollow">7,643,519</a></td>
<td valign="top">Pre-processing and packetizing data in accordance with telecommunication protocol</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,502" target="_blank" rel="nofollow">7,643,502</a></td>
<td valign="top">Method and apparatus to perform frame coalescing</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,477" target="_blank" rel="nofollow">7,643,477</a></td>
<td valign="top">Buffering data packets according to multiple flow control schemes</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,410" target="_blank" rel="nofollow">7,643,410</a></td>
<td valign="top">Method and apparatus for managing a connection in a connection orientated environment</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,275" target="_blank" rel="nofollow">7,643,275</a></td>
<td valign="top">Adjustable portable computer</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,020" target="_blank" rel="nofollow">7,643,020</a></td>
<td valign="top">Driving liquid crystal materials using low voltages</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,791" target="_blank" rel="nofollow">7,642,791</a></td>
<td valign="top">Electronic component/interface interposer</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,764" target="_blank" rel="nofollow">7,642,764</a></td>
<td valign="top">Voltage regulator with loadline based mostly on dynamic current</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,698" target="_blank" rel="nofollow">7,642,698</a></td>
<td valign="top">Dual direction rake piezo actuator</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,610" target="_blank" rel="nofollow">7,642,610</a></td>
<td valign="top">Transistor gate electrode having conductor material layer</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,603" target="_blank" rel="nofollow">7,642,603</a></td>
<td valign="top">Semiconductor device with reduced fringe capacitance</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,641,481" target="_blank" rel="nofollow">7,641,481</a></td>
<td valign="top">Non-intrusive interposer for accessing integrated circuit package signals</td>
</tr>
</table>
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