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<channel>
	<title>Latest Patents</title>
	<link>http://www.latestpatents.com</link>
	<description>Latest Patents of Leading Technology Companies</description>
	<pubDate>Thu, 20 Nov 2008 15:30:28 +0000</pubDate>
	<generator>http://wordpress.org/?v=1.5.2</generator>
	<language>en</language>

		<item>
		<title>Intel patent applications published on 20 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/20/intel-patent-applications-published-on-20-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/20/intel-patent-applications-published-on-20-november-2008/#comments</comments>
		<pubDate>Thu, 20 Nov 2008 15:27:48 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/20/intel-patent-applications-published-on-20-november-2008/</guid>
		<description><![CDATA[	5 US patent applications published on 20 November 2008 and assigned to Intel

	
	
	1
	20080288950
	Concurrent Management of Adaptive Programs
	
	
	2
	20080288872
	Scalable Anti-Replay Windowing
	
	
	3
	20080288848
	Latency by offsetting cyclic redundancy code lanes from data lanes
	
	
	4
	20080283218
	LIQUID COOLING SYSTEM
	
	
	5
	20080282775
	CHAMBER SEALING VALVE
	
	
]]></description>
			<content:encoded><![CDATA[	<p>5 US patent applications published on 20 November 2008 and assigned to Intel<br />
<a id="more-5264"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080288950.PGNR.&#038;OS=DN/20080288950RS=DN/20080288950" target="_blank">20080288950</a></td>
	<td valign="top">Concurrent Management of Adaptive Programs</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080288872.PGNR.&#038;OS=DN/20080288872RS=DN/20080288872" target="_blank">20080288872</a></td>
	<td valign="top">Scalable Anti-Replay Windowing</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080288848.PGNR.&#038;OS=DN/20080288848RS=DN/20080288848" target="_blank">20080288848</a></td>
	<td valign="top">Latency by offsetting cyclic redundancy code lanes from data lanes</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080283218.PGNR.&#038;OS=DN/20080283218RS=DN/20080283218" target="_blank">20080283218</a></td>
	<td valign="top">LIQUID COOLING SYSTEM</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282775.PGNR.&#038;OS=DN/20080282775RS=DN/20080282775" target="_blank">20080282775</a></td>
	<td valign="top">CHAMBER SEALING VALVE</td>
	</tr>
	</table>
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		]]></content:encoded>
			<wfw:commentRSS>http://www.latestpatents.com/2008/11/20/intel-patent-applications-published-on-20-november-2008/feed/</wfw:commentRSS>
	</item>
		<item>
		<title>Intel patents granted on 18 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/18/intel-patents-granted-on-18-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/18/intel-patents-granted-on-18-november-2008/#comments</comments>
		<pubDate>Tue, 18 Nov 2008 13:27:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/11/18/intel-patents-granted-on-18-november-2008/</guid>
		<description><![CDATA[	37 US patents granted on 18 November 2008 and assigned to Intel

	
	
	1
	7,454,756
	Method, apparatus and system for seamlessly sharing devices amongst virtual machines
	
	
	2
	7,454,751
	Fault-tolerant system and methods with trusted message acknowledgement
	
	
	3
	7,454,667
	Techniques to provide information validation and transfer
	
	
	4
	7,454,641
	System powered from a local area network cable
	
	
	5
	7,454,639
	Various apparatuses and methods for reduced power states in system memory
	
	
	6
	7,454,637
	Voltage regulator having reduced [...]]]></description>
			<content:encoded><![CDATA[	<p>37 US patents granted on 18 November 2008 and assigned to Intel<br />
<a id="more-5244"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,756" target="_blank" rel="nofollow">7,454,756</a></td>
	<td valign="top">Method, apparatus and system for seamlessly sharing devices amongst virtual machines</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,751" target="_blank" rel="nofollow">7,454,751</a></td>
	<td valign="top">Fault-tolerant system and methods with trusted message acknowledgement</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,667" target="_blank" rel="nofollow">7,454,667</a></td>
	<td valign="top">Techniques to provide information validation and transfer</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,641" target="_blank" rel="nofollow">7,454,641</a></td>
	<td valign="top">System powered from a local area network cable</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,639" target="_blank" rel="nofollow">7,454,639</a></td>
	<td valign="top">Various apparatuses and methods for reduced power states in system memory</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,637" target="_blank" rel="nofollow">7,454,637</a></td>
	<td valign="top">Voltage regulator having reduced droop</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,632" target="_blank" rel="nofollow">7,454,632</a></td>
	<td valign="top">Reducing computing system power through idle synchronization</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,611" target="_blank" rel="nofollow">7,454,611</a></td>
	<td valign="top">System and method for establishing trust without revealing identity</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,603" target="_blank" rel="nofollow">7,454,603</a></td>
	<td valign="top">Method and system for linking firmware modules in a pre-memory execution environment</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,601" target="_blank" rel="nofollow">7,454,601</a></td>
	<td valign="top">N-wide add-compare-select instruction</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,600" target="_blank" rel="nofollow">7,454,600</a></td>
	<td valign="top">Method and apparatus for assigning thread priority in a processor or the like</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,596" target="_blank" rel="nofollow">7,454,596</a></td>
	<td valign="top">Method and apparatus for partitioned pipelined fetching of multiple execution threads</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,586" target="_blank" rel="nofollow">7,454,586</a></td>
	<td valign="top">Memory device commands</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,576" target="_blank" rel="nofollow">7,454,576</a></td>
	<td valign="top">System and method for cache coherency in a cache with different cache location lengths</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,523" target="_blank" rel="nofollow">7,454,523</a></td>
	<td valign="top">Geographic location determination including inspection of network address</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,511" target="_blank" rel="nofollow">7,454,511</a></td>
	<td valign="top">Visibility of UPNP media renderers and initiating rendering via file system user interface</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,485" target="_blank" rel="nofollow">7,454,485</a></td>
	<td valign="top">Providing uninterrupted media streaming using multiple network sites</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,464" target="_blank" rel="nofollow">7,454,464</a></td>
	<td valign="top">Peer discovery and connection management based on context sensitive social networks</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,342" target="_blank" rel="nofollow">7,454,342</a></td>
	<td valign="top">Coupled hidden Markov model (CHMM) for continuous audiovisual speech recognition</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,341" target="_blank" rel="nofollow">7,454,341</a></td>
	<td valign="top">Method, apparatus, and system for building a compact model for large vocabulary continuous speech recognition (LVCSR) system</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,123" target="_blank" rel="nofollow">7,454,123</a></td>
	<td valign="top">Personal video recorder having reduced overscan coding</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,101" target="_blank" rel="nofollow">7,454,101</a></td>
	<td valign="top">Tunable optical dispersion compensators</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,950" target="_blank" rel="nofollow">7,453,950</a></td>
	<td valign="top">System and method of efficiently modulating data using symbols having more than one pulse</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,946" target="_blank" rel="nofollow">7,453,946</a></td>
	<td valign="top">Communication system and method for channel estimation and beamforming using a multi-element array antenna</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,916" target="_blank" rel="nofollow">7,453,916</a></td>
	<td valign="top">High throughput optical micro-array reader capable of variable pitch and spot size array processing for genomics and proteomics</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,904" target="_blank" rel="nofollow">7,453,904</a></td>
	<td valign="top">Cut-through communication protocol translation bridge</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,870" target="_blank" rel="nofollow">7,453,870</a></td>
	<td valign="top">Backplane for switch fabric</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,797" target="_blank" rel="nofollow">7,453,797</a></td>
	<td valign="top">Method to provide high availability in network elements using distributed architectures</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,622" target="_blank" rel="nofollow">7,453,622</a></td>
	<td valign="top">Micro-electromechanical system (mems) polyelectrolyte gel network pump</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,497" target="_blank" rel="nofollow">7,453,497</a></td>
	<td valign="top">Object trackability via parametric camera tuning</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,469" target="_blank" rel="nofollow">7,453,469</a></td>
	<td valign="top">Slow dither display</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,466" target="_blank" rel="nofollow">7,453,466</a></td>
	<td valign="top">Methods, systems, and data structures for generating a rasterizer</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,144" target="_blank" rel="nofollow">7,453,144</a></td>
	<td valign="top">Thin film capacitors and methods of making the same</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,764" target="_blank" rel="nofollow">7,452,764</a></td>
	<td valign="top">Gate-induced strain for MOS performance improvement</td>
	</tr>
	<tr>
	<td valign="top" align="right">35</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,728" target="_blank" rel="nofollow">7,452,728</a></td>
	<td valign="top">Metal ion separation from aqueous solutions using photoswitchable ionophores</td>
	</tr>
	<tr>
	<td valign="top" align="right">36</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,637" target="_blank" rel="nofollow">7,452,637</a></td>
	<td valign="top">Method and apparatus for clean photomask handling</td>
	</tr>
	<tr>
	<td valign="top" align="right">37</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,139" target="_blank" rel="nofollow">7,452,139</a></td>
	<td valign="top">Aligning lens carriers and ferrules with alignment frames</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 13 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/13/intel-patent-applications-published-on-13-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/13/intel-patent-applications-published-on-13-november-2008/#comments</comments>
		<pubDate>Thu, 13 Nov 2008 14:20:05 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/13/intel-patent-applications-published-on-13-november-2008/</guid>
		<description><![CDATA[	6 US patent applications published on 13 November 2008 and assigned to Intel

	
	
	1
	20080282358
	Protecting Caller Function from Undesired Access by Callee Function
	
	
	2
	20080282257
	Transient Fault Detection by Integrating an SRMT Code and a Non SRMT Code in a Single Application
	
	
	3
	20080282241
	Method and Apparatus to Support Virtualization with Code Patches
	
	
	4
	20080282116
	Transient Fault Detection by Integrating an SRMT Code and a Non [...]]]></description>
			<content:encoded><![CDATA[	<p>6 US patent applications published on 13 November 2008 and assigned to Intel<br />
<a id="more-5224"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282358.PGNR.&#038;OS=DN/20080282358RS=DN/20080282358" target="_blank">20080282358</a></td>
	<td valign="top">Protecting Caller Function from Undesired Access by Callee Function</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282257.PGNR.&#038;OS=DN/20080282257RS=DN/20080282257" target="_blank">20080282257</a></td>
	<td valign="top">Transient Fault Detection by Integrating an SRMT Code and a Non SRMT Code in a Single Application</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282241.PGNR.&#038;OS=DN/20080282241RS=DN/20080282241" target="_blank">20080282241</a></td>
	<td valign="top">Method and Apparatus to Support Virtualization with Code Patches</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282116.PGNR.&#038;OS=DN/20080282116RS=DN/20080282116" target="_blank">20080282116</a></td>
	<td valign="top">Transient Fault Detection by Integrating an SRMT Code and a Non SRMT Code in a Single Application</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080280593.PGNR.&#038;OS=DN/20080280593RS=DN/20080280593" target="_blank">20080280593</a></td>
	<td valign="top">Protecting Caller Function from Undesired Access by Callee Function</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080280395.PGNR.&#038;OS=DN/20080280395RS=DN/20080280395" target="_blank">20080280395</a></td>
	<td valign="top">Semiconducting device with stacked dice</td>
	</tr>
	</table>
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		]]></content:encoded>
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	</item>
		<item>
		<title>Intel patents granted on 11 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/11/intel-patents-granted-on-11-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/11/intel-patents-granted-on-11-november-2008/#comments</comments>
		<pubDate>Wed, 12 Nov 2008 00:08:22 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/11/11/intel-patents-granted-on-11-november-2008/</guid>
		<description><![CDATA[	38 US patents granted on 11 November 2008 and assigned to Intel

	
	
	1
	RE40,567
	Flash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation
	
	
	2
	7,451,454
	Event handling mechanism
	
	
	3
	7,451,353
	Cache disassociation detection
	
	
	4
	7,451,338
	Clock domain crossing
	
	
	5
	7,451,333
	Coordinating idle state transitions in multi-core processors
	
	
	6
	7,451,301
	OS independent device management methods and apparatuses having a map providing codes for various [...]]]></description>
			<content:encoded><![CDATA[	<p>38 US patents granted on 11 November 2008 and assigned to Intel<br />
<a id="more-5204"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=RE40,567" target="_blank" rel="nofollow">RE40,567</a></td>
	<td valign="top">Flash memory device of capable of sensing a threshold voltage of memory cells on a page mode of operation</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,454" target="_blank" rel="nofollow">7,451,454</a></td>
	<td valign="top">Event handling mechanism</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,353" target="_blank" rel="nofollow">7,451,353</a></td>
	<td valign="top">Cache disassociation detection</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,338" target="_blank" rel="nofollow">7,451,338</a></td>
	<td valign="top">Clock domain crossing</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,333" target="_blank" rel="nofollow">7,451,333</a></td>
	<td valign="top">Coordinating idle state transitions in multi-core processors</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,301" target="_blank" rel="nofollow">7,451,301</a></td>
	<td valign="top">OS independent device management methods and apparatuses having a map providing codes for various activations of keys</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,296" target="_blank" rel="nofollow">7,451,296</a></td>
	<td valign="top">Method and apparatus for pausing execution in a processor or the like</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,295" target="_blank" rel="nofollow">7,451,295</a></td>
	<td valign="top">Early data return indication mechanism for data cache to detect readiness of data via an early data ready indication by scheduling, rescheduling, and replaying of requests in request queues</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,294" target="_blank" rel="nofollow">7,451,294</a></td>
	<td valign="top">Apparatus and method for two micro-operation flow using source override</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,255" target="_blank" rel="nofollow">7,451,255</a></td>
	<td valign="top">Hardware port scheduler (PTS) having register to indicate which of plurality of protocol engines PTS is to support</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,207" target="_blank" rel="nofollow">7,451,207</a></td>
	<td valign="top">Predictive provisioning of media resources</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,197" target="_blank" rel="nofollow">7,451,197</a></td>
	<td valign="top">Method, system, and article of manufacture for network protocols</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,182" target="_blank" rel="nofollow">7,451,182</a></td>
	<td valign="top">Coordinating operations of network and host processors</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,169" target="_blank" rel="nofollow">7,451,169</a></td>
	<td valign="top">Method and apparatus for providing packed shift operations in a processor</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,121" target="_blank" rel="nofollow">7,451,121</a></td>
	<td valign="top">Genetic algorithm for microcode compression</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,939" target="_blank" rel="nofollow">7,450,939</a></td>
	<td valign="top">Internet base station with a telephone line</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,858" target="_blank" rel="nofollow">7,450,858</a></td>
	<td valign="top">Apparatus and method for transmitting and receiving wavelength division multiplexing signals</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,798" target="_blank" rel="nofollow">7,450,798</a></td>
	<td valign="top">Automatic shutdown system and method for optical multiplexers and demultiplexers</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,796" target="_blank" rel="nofollow">7,450,796</a></td>
	<td valign="top">Radiation switch</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,655" target="_blank" rel="nofollow">7,450,655</a></td>
	<td valign="top">Timing error detection for a digital receiver</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,631" target="_blank" rel="nofollow">7,450,631</a></td>
	<td valign="top">Metric correction for multi user detection, for long codes DS-CDMA</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,593" target="_blank" rel="nofollow">7,450,593</a></td>
	<td valign="top">Clock difference compensation for a network</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,588" target="_blank" rel="nofollow">7,450,588</a></td>
	<td valign="top">Storage network out of order packet reordering mechanism</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,576" target="_blank" rel="nofollow">7,450,576</a></td>
	<td valign="top">Timeslot assignment</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,489" target="_blank" rel="nofollow">7,450,489</a></td>
	<td valign="top">Multiple-antenna communication systems and methods for communicating in wireless local area networks that include single-antenna communication devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,456" target="_blank" rel="nofollow">7,450,456</a></td>
	<td valign="top">Temperature determination and communication for multiple devices of a memory module</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,396" target="_blank" rel="nofollow">7,450,396</a></td>
	<td valign="top">Skew compensation by changing ground parasitic for traces</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,131" target="_blank" rel="nofollow">7,450,131</a></td>
	<td valign="top">Memory layout for re-ordering instructions using pointers</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,966" target="_blank" rel="nofollow">7,449,966</a></td>
	<td valign="top">Method and an apparatus to sense supply voltage</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,919" target="_blank" rel="nofollow">7,449,919</a></td>
	<td valign="top">Driver circuit bias control</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,904" target="_blank" rel="nofollow">7,449,904</a></td>
	<td valign="top">Integrated circuit burn-in methods and apparatus</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,871" target="_blank" rel="nofollow">7,449,871</a></td>
	<td valign="top">System for setting an electrical circuit parameter at a predetermined value</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,780" target="_blank" rel="nofollow">7,449,780</a></td>
	<td valign="top">Apparatus to minimize thermal impedance using copper on die backside</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,756" target="_blank" rel="nofollow">7,449,756</a></td>
	<td valign="top">Semiconductor device with a high-k gate dielectric and a metal gate electrode</td>
	</tr>
	<tr>
	<td valign="top" align="right">35</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,743" target="_blank" rel="nofollow">7,449,743</a></td>
	<td valign="top">Control gate profile for flash technology</td>
	</tr>
	<tr>
	<td valign="top" align="right">36</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,373" target="_blank" rel="nofollow">7,449,373</a></td>
	<td valign="top">Method of ion implanting for tri-gate devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">37</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,361" target="_blank" rel="nofollow">7,449,361</a></td>
	<td valign="top">Semiconductor substrate with islands of diamond and resulting devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">38</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,264" target="_blank" rel="nofollow">7,449,264</a></td>
	<td valign="top">Compensation of reflective mask effects in lithography systems</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 06 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/06/intel-patent-applications-published-on-06-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/06/intel-patent-applications-published-on-06-november-2008/#comments</comments>
		<pubDate>Thu, 06 Nov 2008 13:47:28 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/06/intel-patent-applications-published-on-06-november-2008/</guid>
		<description><![CDATA[	1 US patent application published on 06 November 2008 and assigned to Intel

	
	
	1
	20080273580
	DYNAMIC ALLOCATION OF CYCLIC EXTENSION IN ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING SYSTEMS
	
	
]]></description>
			<content:encoded><![CDATA[	<p>1 US patent application published on 06 November 2008 and assigned to Intel<br />
<a id="more-5184"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080273580.PGNR.&#038;OS=DN/20080273580RS=DN/20080273580" target="_blank">20080273580</a></td>
	<td valign="top">DYNAMIC ALLOCATION OF CYCLIC EXTENSION IN ORTHOGONAL FREQUENCY DIVISION MULTIPLEXING SYSTEMS</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patents granted on 04 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/04/intel-patents-granted-on-04-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/04/intel-patents-granted-on-04-november-2008/#comments</comments>
		<pubDate>Tue, 04 Nov 2008 11:36:06 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/11/04/intel-patents-granted-on-04-november-2008/</guid>
		<description><![CDATA[	38 US patents granted on 04 November 2008 and assigned to Intel

	
	
	1
	7,448,067
	Method and apparatus for enforcing network security policies
	
	
	2
	7,448,031
	Methods and apparatus to compile a software program to manage parallel .mu.caches
	
	
	3
	7,448,030
	Optimized ordering of firmware modules in pre-boot environment
	
	
	4
	7,448,025
	Qualification of event detection by thread ID and thread privilege level
	
	
	5
	7,447,979
	Device, system and method of detecting erroneous packets
	
	
	6
	7,447,953
	Lane testing [...]]]></description>
			<content:encoded><![CDATA[	<p>38 US patents granted on 04 November 2008 and assigned to Intel<br />
<a id="more-5164"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,448,067" target="_blank" rel="nofollow">7,448,067</a></td>
	<td valign="top">Method and apparatus for enforcing network security policies</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,448,031" target="_blank" rel="nofollow">7,448,031</a></td>
	<td valign="top">Methods and apparatus to compile a software program to manage parallel .mu.caches</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,448,030" target="_blank" rel="nofollow">7,448,030</a></td>
	<td valign="top">Optimized ordering of firmware modules in pre-boot environment</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,448,025" target="_blank" rel="nofollow">7,448,025</a></td>
	<td valign="top">Qualification of event detection by thread ID and thread privilege level</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,979" target="_blank" rel="nofollow">7,447,979</a></td>
	<td valign="top">Device, system and method of detecting erroneous packets</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,953" target="_blank" rel="nofollow">7,447,953</a></td>
	<td valign="top">Lane testing with variable mapping</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,948" target="_blank" rel="nofollow">7,447,948</a></td>
	<td valign="top">ECC coding for high speed implementation</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,929" target="_blank" rel="nofollow">7,447,929</a></td>
	<td valign="top">Countering power resonance</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,918" target="_blank" rel="nofollow">7,447,918</a></td>
	<td valign="top">Method, apparatus and system for enabling a new data processing device operating state</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,877" target="_blank" rel="nofollow">7,447,877</a></td>
	<td valign="top">Method and apparatus for converting memory instructions to prefetch operations during a thread switch window</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,826" target="_blank" rel="nofollow">7,447,826</a></td>
	<td valign="top">Receive buffer in a data storage system</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,820" target="_blank" rel="nofollow">7,447,820</a></td>
	<td valign="top">Retargeting of platform interrupts</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,810" target="_blank" rel="nofollow">7,447,810</a></td>
	<td valign="top">Implementing bufferless Direct Memory Access (DMA) controllers using split transactions</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,727" target="_blank" rel="nofollow">7,447,727</a></td>
	<td valign="top">Recursive carry-select topology in incrementer designs</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,512" target="_blank" rel="nofollow">7,447,512</a></td>
	<td valign="top">Method and system for allocation of resources within wireless systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,382" target="_blank" rel="nofollow">7,447,382</a></td>
	<td valign="top">Computing a higher resolution image from multiple lower resolution images using model-based, robust Bayesian estimation</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,358" target="_blank" rel="nofollow">7,447,358</a></td>
	<td valign="top">Image segmentation using branch and bound analysis</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,268" target="_blank" rel="nofollow">7,447,268</a></td>
	<td valign="top">OFDM system with per subcarrier phase rotation</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,263" target="_blank" rel="nofollow">7,447,263</a></td>
	<td valign="top">Processing digital data prior to compression</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,233" target="_blank" rel="nofollow">7,447,233</a></td>
	<td valign="top">Packet aggregation protocol for advanced switching</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,232" target="_blank" rel="nofollow">7,447,232</a></td>
	<td valign="top">Data burst transmission methods in WLAN devices and systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,229" target="_blank" rel="nofollow">7,447,229</a></td>
	<td valign="top">Method for providing prioritized data movement between endpoints connected by multiple logical channels</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,208" target="_blank" rel="nofollow">7,447,208</a></td>
	<td valign="top">Configuration access mechanism for packet switching architecture</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,185" target="_blank" rel="nofollow">7,447,185</a></td>
	<td valign="top">Transmitting and protecting long frames in a wireless local area network</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,177" target="_blank" rel="nofollow">7,447,177</a></td>
	<td valign="top">Method and apparatus of secure roaming</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,155" target="_blank" rel="nofollow">7,447,155</a></td>
	<td valign="top">Guaranteed service in a data network</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,054" target="_blank" rel="nofollow">7,447,054</a></td>
	<td valign="top">NBTI-resilient memory cells with NAND gates</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,873" target="_blank" rel="nofollow">7,446,873</a></td>
	<td valign="top">Reflective alignment grating</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,820" target="_blank" rel="nofollow">7,446,820</a></td>
	<td valign="top">Methods and apparatus for re-scaling image by variable re-scaling factor using B-spline interpolator</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,743" target="_blank" rel="nofollow">7,446,743</a></td>
	<td valign="top">Compensating organic light emitting device displays for temperature effects</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,660" target="_blank" rel="nofollow">7,446,660</a></td>
	<td valign="top">Passive environmental RFID transceiver</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,572" target="_blank" rel="nofollow">7,446,572</a></td>
	<td valign="top">Method and system for a configurable Vcc reference and Vss reference differential current mode transmitter</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,412" target="_blank" rel="nofollow">7,446,412</a></td>
	<td valign="top">Heat sink design using clad metal</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,382" target="_blank" rel="nofollow">7,446,382</a></td>
	<td valign="top">Method and apparatus for fabrication of passivated microfluidic structures in semiconductor substrates</td>
	</tr>
	<tr>
	<td valign="top" align="right">35</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,360" target="_blank" rel="nofollow">7,446,360</a></td>
	<td valign="top">Polymer device with a nanocomposite barrier layer</td>
	</tr>
	<tr>
	<td valign="top" align="right">36</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,329" target="_blank" rel="nofollow">7,446,329</a></td>
	<td valign="top">Erosion resistance of EUV source electrodes</td>
	</tr>
	<tr>
	<td valign="top" align="right">37</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,046" target="_blank" rel="nofollow">7,446,046</a></td>
	<td valign="top">Selective polish for fabricating electronic devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">38</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,980" target="_blank" rel="nofollow">7,445,980</a></td>
	<td valign="top">Method and apparatus for improving stability of a 6T CMOS SRAM cell</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 30 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/30/intel-patent-applications-published-on-30-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/30/intel-patent-applications-published-on-30-october-2008/#comments</comments>
		<pubDate>Thu, 30 Oct 2008 14:45:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/30/intel-patent-applications-published-on-30-october-2008/</guid>
		<description><![CDATA[	10 US patent applications published on 30 October 2008 and assigned to Intel

	
	
	1
	20080270041
	SYSTEM AND METHOD FOR BROAD-BASED MULTIPLE SCLEROSIS ASSOCIATION GENE TRANSCRIPT TEST
	
	
	2
	20080269063
	METHOD AND SYSTEM FOR PREPARING A MICROARRAY FOR A DISEASE ASSOCIATION GENE TRANSCRIPT TEST
	
	
	3
	20080268670
	SELF-BALANCED DUAL L-SHAPED SOCKET
	
	
	4
	20080268443
	BROAD-BASED DISEASE ASSOCIATION FROM A GENE TRANSCRIPT TEST
	
	
	5
	20080268442
	METHOD AND SYSTEM FOR PREPARING A BLOOD SAMPLE FOR A [...]]]></description>
			<content:encoded><![CDATA[	<p>10 US patent applications published on 30 October 2008 and assigned to Intel<br />
<a id="more-5144"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080270041.PGNR.&#038;OS=DN/20080270041RS=DN/20080270041" target="_blank">20080270041</a></td>
	<td valign="top">SYSTEM AND METHOD FOR BROAD-BASED MULTIPLE SCLEROSIS ASSOCIATION GENE TRANSCRIPT TEST</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080269063.PGNR.&#038;OS=DN/20080269063RS=DN/20080269063" target="_blank">20080269063</a></td>
	<td valign="top">METHOD AND SYSTEM FOR PREPARING A MICROARRAY FOR A DISEASE ASSOCIATION GENE TRANSCRIPT TEST</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080268670.PGNR.&#038;OS=DN/20080268670RS=DN/20080268670" target="_blank">20080268670</a></td>
	<td valign="top">SELF-BALANCED DUAL L-SHAPED SOCKET</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080268443.PGNR.&#038;OS=DN/20080268443RS=DN/20080268443" target="_blank">20080268443</a></td>
	<td valign="top">BROAD-BASED DISEASE ASSOCIATION FROM A GENE TRANSCRIPT TEST</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080268442.PGNR.&#038;OS=DN/20080268442RS=DN/20080268442" target="_blank">20080268442</a></td>
	<td valign="top">METHOD AND SYSTEM FOR PREPARING A BLOOD SAMPLE FOR A DISEASE ASSOCIATION GENE TRANSCRIPT TEST</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080267633.PGNR.&#038;OS=DN/20080267633RS=DN/20080267633" target="_blank">20080267633</a></td>
	<td valign="top">SPLIT EQUALIZATION FUNCTION FOR OPTICAL AND ELECTRICAL MODULES</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080267387.PGNR.&#038;OS=DN/20080267387RS=DN/20080267387" target="_blank">20080267387</a></td>
	<td valign="top">METHOD AND APPARATUS FOR IMPLEMENTING CALL PROCESSING IN PACKET TELEPHONY NETWORKS</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266778.PGNR.&#038;OS=DN/20080266778RS=DN/20080266778" target="_blank">20080266778</a></td>
	<td valign="top">Memory module routing</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266017.PGNR.&#038;OS=DN/20080266017RS=DN/20080266017" target="_blank">20080266017</a></td>
	<td valign="top">CONTROLLING COUPLING STRENGTH IN ELECTROMAGNETIC BUS COUPLING</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080265407.PGNR.&#038;OS=DN/20080265407RS=DN/20080265407" target="_blank">20080265407</a></td>
	<td valign="top">WAFER-LEVEL BONDING FOR MECHANICALLY REINFORCED ULTRA-THIN DIE</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patents granted on 28 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/28/intel-patents-granted-on-28-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/28/intel-patents-granted-on-28-october-2008/#comments</comments>
		<pubDate>Tue, 28 Oct 2008 21:24:12 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/10/28/intel-patents-granted-on-28-october-2008/</guid>
		<description><![CDATA[	29 US patents granted on 28 October 2008 and assigned to Intel

	
	
	1
	7,444,667
	Method and apparatus for trusted blade device computing
	
	
	2
	7,444,642
	Method for indicating completion status of asynchronous events
	
	
	3
	7,444,558
	Programmable measurement mode for a serial point to point link
	
	
	4
	7,444,528
	Component reliability budgeting system
	
	
	5
	7,444,524
	Dynamic voltage transitions
	
	
	6
	7,444,512
	Establishing trust without revealing identity
	
	
	7
	7,444,507
	Method and apparatus for distribution of digital certificates
	
	
	8
	7,444,497
	Managing external memory updates for [...]]]></description>
			<content:encoded><![CDATA[	<p>29 US patents granted on 28 October 2008 and assigned to Intel<br />
<a id="more-5124"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,667" target="_blank" rel="nofollow">7,444,667</a></td>
	<td valign="top">Method and apparatus for trusted blade device computing</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,642" target="_blank" rel="nofollow">7,444,642</a></td>
	<td valign="top">Method for indicating completion status of asynchronous events</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,558" target="_blank" rel="nofollow">7,444,558</a></td>
	<td valign="top">Programmable measurement mode for a serial point to point link</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,528" target="_blank" rel="nofollow">7,444,528</a></td>
	<td valign="top">Component reliability budgeting system</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,524" target="_blank" rel="nofollow">7,444,524</a></td>
	<td valign="top">Dynamic voltage transitions</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,512" target="_blank" rel="nofollow">7,444,512</a></td>
	<td valign="top">Establishing trust without revealing identity</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,507" target="_blank" rel="nofollow">7,444,507</a></td>
	<td valign="top">Method and apparatus for distribution of digital certificates</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,497" target="_blank" rel="nofollow">7,444,497</a></td>
	<td valign="top">Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,493" target="_blank" rel="nofollow">7,444,493</a></td>
	<td valign="top">Address translation for input/output devices using hierarchical translation tables</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,457" target="_blank" rel="nofollow">7,444,457</a></td>
	<td valign="top">Retrieving data blocks with reduced linear addresses</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,438" target="_blank" rel="nofollow">7,444,438</a></td>
	<td valign="top">Method and architecture to support interaction between a host computer and remote devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,408" target="_blank" rel="nofollow">7,444,408</a></td>
	<td valign="top">Network data analysis and characterization model for implementation of secure enclaves within large corporate networks</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,366" target="_blank" rel="nofollow">7,444,366</a></td>
	<td valign="top">Faster shift value calculation using modified carry-lookahead adder</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,319" target="_blank" rel="nofollow">7,444,319</a></td>
	<td valign="top">Method and apparatus for extracting relevant content based on user preferences indicated by user actions</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,869" target="_blank" rel="nofollow">7,443,869</a></td>
	<td valign="top">Deadlock avoidance queuing mechanism</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,854" target="_blank" rel="nofollow">7,443,854</a></td>
	<td valign="top">Methods and apparatus to route packets in a policy driven networked environment</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,848" target="_blank" rel="nofollow">7,443,848</a></td>
	<td valign="top">External device-based prefetching mechanism</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,836" target="_blank" rel="nofollow">7,443,836</a></td>
	<td valign="top">Processing a data packet</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,818" target="_blank" rel="nofollow">7,443,818</a></td>
	<td valign="top">Method, apparatus and system of multiple-input-multiple-output wireless communication</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,670" target="_blank" rel="nofollow">7,443,670</a></td>
	<td valign="top">Systems for improved blower fans</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,204" target="_blank" rel="nofollow">7,443,204</a></td>
	<td valign="top">Common-mode noise-reduced output transmitter</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,184" target="_blank" rel="nofollow">7,443,184</a></td>
	<td valign="top">Apparatus and methods for self-heating burn-in processes</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,173" target="_blank" rel="nofollow">7,443,173</a></td>
	<td valign="top">Systems and techniques for radio frequency noise cancellation</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,030" target="_blank" rel="nofollow">7,443,030</a></td>
	<td valign="top">Thin silicon based substrate</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,983" target="_blank" rel="nofollow">7,442,983</a></td>
	<td valign="top">Method for making a semiconductor device having a high-k gate dielectric</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,675" target="_blank" rel="nofollow">7,442,675</a></td>
	<td valign="top">Cleaning composition and method of cleaning semiconductor substrate</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,634" target="_blank" rel="nofollow">7,442,634</a></td>
	<td valign="top">Method for constructing contact formations</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,487" target="_blank" rel="nofollow">7,442,487</a></td>
	<td valign="top">Low outgassing and non-crosslinking series of polymers for EUV negative tone photoresists</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,339" target="_blank" rel="nofollow">7,442,339</a></td>
	<td valign="top">Microfluidic apparatus, Raman spectroscopy systems, and methods for performing molecular reactions</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 23 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/23/intel-patent-applications-published-on-23-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/23/intel-patent-applications-published-on-23-october-2008/#comments</comments>
		<pubDate>Thu, 23 Oct 2008 15:38:10 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/23/intel-patent-applications-published-on-23-october-2008/</guid>
		<description><![CDATA[	2 US patent applications published on 23 October 2008 and assigned to Intel

	
	
	1
	20080263416
	METHOD AND APPARATUS TO ADJUST VOLTAGE FOR STORAGE LOCATION RELIABILITY
	
	
	2
	20080259804
	DEVICE AND METHODS FOR INCREASING WIRELESS CONNECTION SPEEDS
	
	
]]></description>
			<content:encoded><![CDATA[	<p>2 US patent applications published on 23 October 2008 and assigned to Intel<br />
<a id="more-5104"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080263416.PGNR.&#038;OS=DN/20080263416RS=DN/20080263416" target="_blank">20080263416</a></td>
	<td valign="top">METHOD AND APPARATUS TO ADJUST VOLTAGE FOR STORAGE LOCATION RELIABILITY</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080259804.PGNR.&#038;OS=DN/20080259804RS=DN/20080259804" target="_blank">20080259804</a></td>
	<td valign="top">DEVICE AND METHODS FOR INCREASING WIRELESS CONNECTION SPEEDS</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patents granted on 21 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/21/intel-patents-granted-on-21-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/21/intel-patents-granted-on-21-october-2008/#comments</comments>
		<pubDate>Tue, 21 Oct 2008 13:24:41 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/10/21/intel-patents-granted-on-21-october-2008/</guid>
		<description><![CDATA[	34 US patents granted on 21 October 2008 and assigned to Intel

	
	
	1
	7,441,272
	Techniques for self-isolation of networked devices
	
	
	2
	7,441,270
	Connectivity in the presence of barriers
	
	
	3
	7,441,245
	Phasing for a multi-threaded network processor
	
	
	4
	7,441,179
	Determining a checksum from packet data
	
	
	5
	7,441,146
	RAID write completion apparatus, systems, and methods
	
	
	6
	7,441,132
	Circuit for enabling dual mode safe power-on sequencing
	
	
	7
	7,441,112
	Offloading the processing of a network protocol stack
	
	
	8
	7,441,107
	Utilizing an advanced load [...]]]></description>
			<content:encoded><![CDATA[	<p>34 US patents granted on 21 October 2008 and assigned to Intel<br />
<a id="more-5084"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,272" target="_blank" rel="nofollow">7,441,272</a></td>
	<td valign="top">Techniques for self-isolation of networked devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,270" target="_blank" rel="nofollow">7,441,270</a></td>
	<td valign="top">Connectivity in the presence of barriers</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,245" target="_blank" rel="nofollow">7,441,245</a></td>
	<td valign="top">Phasing for a multi-threaded network processor</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,179" target="_blank" rel="nofollow">7,441,179</a></td>
	<td valign="top">Determining a checksum from packet data</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,146" target="_blank" rel="nofollow">7,441,146</a></td>
	<td valign="top">RAID write completion apparatus, systems, and methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,132" target="_blank" rel="nofollow">7,441,132</a></td>
	<td valign="top">Circuit for enabling dual mode safe power-on sequencing</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,112" target="_blank" rel="nofollow">7,441,112</a></td>
	<td valign="top">Offloading the processing of a network protocol stack</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,107" target="_blank" rel="nofollow">7,441,107</a></td>
	<td valign="top">Utilizing an advanced load address table for memory disambiguation in an out of order processor</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,093" target="_blank" rel="nofollow">7,441,093</a></td>
	<td valign="top">Segmentation management using a rolling window technique</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,069" target="_blank" rel="nofollow">7,441,069</a></td>
	<td valign="top">Default instruction to hide nonvolatile memory core initialization latency</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,055" target="_blank" rel="nofollow">7,441,055</a></td>
	<td valign="top">Apparatus and method to maximize buffer utilization in an I/O controller</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,998" target="_blank" rel="nofollow">7,440,998</a></td>
	<td valign="top">Provisioning for a modular server</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,994" target="_blank" rel="nofollow">7,440,994</a></td>
	<td valign="top">Method and apparatus for peer-to-peer services to shift network traffic to allow for an efficient transfer of information between devices via prioritized list</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,730" target="_blank" rel="nofollow">7,440,730</a></td>
	<td valign="top">Device, system and method of multiple transceivers control</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,632" target="_blank" rel="nofollow">7,440,632</a></td>
	<td valign="top">Technique for performing error diffusion</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,584" target="_blank" rel="nofollow">7,440,584</a></td>
	<td valign="top">System and method for marking data and document distribution</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,526" target="_blank" rel="nofollow">7,440,526</a></td>
	<td valign="top">Method and apparatus to acquire frame within transmission</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,510" target="_blank" rel="nofollow">7,440,510</a></td>
	<td valign="top">Multicarrier transmitter, multicarrier receiver, and methods for communicating multiple spatial signal streams</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,466" target="_blank" rel="nofollow">7,440,466</a></td>
	<td valign="top">Method, apparatus and system for accessing multiple nodes on a private network</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,461" target="_blank" rel="nofollow">7,440,461</a></td>
	<td valign="top">Methods and apparatus for detecting patterns in a data stream</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,423" target="_blank" rel="nofollow">7,440,423</a></td>
	<td valign="top">Channel specification apparatus, systems, and methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,986" target="_blank" rel="nofollow">7,439,986</a></td>
	<td valign="top">Pixel filtering using shared filter resource between overlay and texture mapping engines</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,804" target="_blank" rel="nofollow">7,439,804</a></td>
	<td valign="top">Amplifier with level shifting feedback network</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,788" target="_blank" rel="nofollow">7,439,788</a></td>
	<td valign="top">Receive clock deskewing method, apparatus, and system</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,618" target="_blank" rel="nofollow">7,439,618</a></td>
	<td valign="top">Integrated circuit thermal management method and apparatus</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,617" target="_blank" rel="nofollow">7,439,617</a></td>
	<td valign="top">Capillary underflow integral heat spreader</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,608" target="_blank" rel="nofollow">7,439,608</a></td>
	<td valign="top">Symmetric bipolar junction transistor design for deep sub-micron fabrication processes</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,588" target="_blank" rel="nofollow">7,439,588</a></td>
	<td valign="top">Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,571" target="_blank" rel="nofollow">7,439,571</a></td>
	<td valign="top">Method for fabricating metal gate structures</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,179" target="_blank" rel="nofollow">7,439,179</a></td>
	<td valign="top">Healing detrimental bonds in deposited materials</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,113" target="_blank" rel="nofollow">7,439,113</a></td>
	<td valign="top">Forming dual metal complementary metal oxide semiconductor integrated circuits</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,438,997" target="_blank" rel="nofollow">7,438,997</a></td>
	<td valign="top">Imaging and devices in lithography</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,438,794" target="_blank" rel="nofollow">7,438,794</a></td>
	<td valign="top">Method of copper electroplating to improve gapfill</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,438,580" target="_blank" rel="nofollow">7,438,580</a></td>
	<td valign="top">Intermediate load mechanism for a semiconductor package</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 16 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/16/intel-patent-applications-published-on-16-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/16/intel-patent-applications-published-on-16-october-2008/#comments</comments>
		<pubDate>Thu, 16 Oct 2008 11:04:25 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/16/intel-patent-applications-published-on-16-october-2008/</guid>
		<description><![CDATA[	4 US patent applications published on 16 October 2008 and assigned to Intel

	
	
	1
	20080256532
	Installing and Executing Shared Applications in Shared Folders
	
	
	2
	20080254611
	INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE
	
	
	3
	20080254605
	METHOD OF REDUCING THE INTERFACIAL OXIDE THICKNESS
	
	
	4
	20080253471
	SYSTEMS AND METHODS FOR ADAPTIVE BIT LOADING IN A MULTIPLE ANTENNA ORTHOGONAL FREQUENCY DIVISION MULTIPLEXED COMMUNICATION SYSTEM
	
	
]]></description>
			<content:encoded><![CDATA[	<p>4 US patent applications published on 16 October 2008 and assigned to Intel<br />
<a id="more-5064"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080256532.PGNR.&#038;OS=DN/20080256532RS=DN/20080256532" target="_blank">20080256532</a></td>
	<td valign="top">Installing and Executing Shared Applications in Shared Folders</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080254611.PGNR.&#038;OS=DN/20080254611RS=DN/20080254611" target="_blank">20080254611</a></td>
	<td valign="top">INTERCONNECTION DESIGNS AND MATERIALS HAVING IMPROVED STRENGTH AND FATIGUE LIFE</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080254605.PGNR.&#038;OS=DN/20080254605RS=DN/20080254605" target="_blank">20080254605</a></td>
	<td valign="top">METHOD OF REDUCING THE INTERFACIAL OXIDE THICKNESS</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080253471.PGNR.&#038;OS=DN/20080253471RS=DN/20080253471" target="_blank">20080253471</a></td>
	<td valign="top">SYSTEMS AND METHODS FOR ADAPTIVE BIT LOADING IN A MULTIPLE ANTENNA ORTHOGONAL FREQUENCY DIVISION MULTIPLEXED COMMUNICATION SYSTEM</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patents granted on 14 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/14/intel-patents-granted-on-14-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/14/intel-patents-granted-on-14-october-2008/#comments</comments>
		<pubDate>Tue, 14 Oct 2008 16:09:39 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/10/14/intel-patents-granted-on-14-october-2008/</guid>
		<description><![CDATA[	44 US patents granted on 14 October 2008 and assigned to Intel

	
	
	1
	7,437,738
	Method, system, and program for interfacing with a network adaptor supporting a plurality of devices
	
	
	2
	7,437,724
	Registers for data transfers
	
	
	3
	7,437,719
	Combinational approach for developing building blocks of DSP compiler
	
	
	4
	7,437,666
	Expression grouping and evaluation
	
	
	5
	7,437,643
	Automated BIST execution scheme for a link
	
	
	6
	7,437,634
	Test scan cells
	
	
	7
	7,437,613
	Protecting an operating system kernel from third party [...]]]></description>
			<content:encoded><![CDATA[	<p>44 US patents granted on 14 October 2008 and assigned to Intel<br />
<a id="more-5044"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,738" target="_blank" rel="nofollow">7,437,738</a></td>
	<td valign="top">Method, system, and program for interfacing with a network adaptor supporting a plurality of devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,724" target="_blank" rel="nofollow">7,437,724</a></td>
	<td valign="top">Registers for data transfers</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,719" target="_blank" rel="nofollow">7,437,719</a></td>
	<td valign="top">Combinational approach for developing building blocks of DSP compiler</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,666" target="_blank" rel="nofollow">7,437,666</a></td>
	<td valign="top">Expression grouping and evaluation</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,643" target="_blank" rel="nofollow">7,437,643</a></td>
	<td valign="top">Automated BIST execution scheme for a link</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,634" target="_blank" rel="nofollow">7,437,634</a></td>
	<td valign="top">Test scan cells</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,613" target="_blank" rel="nofollow">7,437,613</a></td>
	<td valign="top">Protecting an operating system kernel from third party drivers</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,581" target="_blank" rel="nofollow">7,437,581</a></td>
	<td valign="top">Method and apparatus for varying energy per instruction according to the amount of available parallelism</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,546" target="_blank" rel="nofollow">7,437,546</a></td>
	<td valign="top">Multiple, cooperating operating systems (OS) platform system and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,542" target="_blank" rel="nofollow">7,437,542</a></td>
	<td valign="top">Identifying and processing essential and non-essential code separately</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,531" target="_blank" rel="nofollow">7,437,531</a></td>
	<td valign="top">Testing memories</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,518" target="_blank" rel="nofollow">7,437,518</a></td>
	<td valign="top">Hiding conflict, coherence completion and transaction ID elements of a coherence protocol</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,510" target="_blank" rel="nofollow">7,437,510</a></td>
	<td valign="top">Instruction-assisted cache management for efficient use of cache and memory</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,503" target="_blank" rel="nofollow">7,437,503</a></td>
	<td valign="top">Method and apparatus for handling data transfers</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,501" target="_blank" rel="nofollow">7,437,501</a></td>
	<td valign="top">Combining the address-mapping and page-referencing steps in a memory controller</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,499" target="_blank" rel="nofollow">7,437,499</a></td>
	<td valign="top">Dividing a flash memory operation into phases</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,474" target="_blank" rel="nofollow">7,437,474</a></td>
	<td valign="top">Proxy-less packet routing between private and public address realms</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,398" target="_blank" rel="nofollow">7,437,398</a></td>
	<td valign="top">Pattern matching architecture</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,396" target="_blank" rel="nofollow">7,437,396</a></td>
	<td valign="top">Apparatus and method for generating transforms</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,286" target="_blank" rel="nofollow">7,437,286</a></td>
	<td valign="top">Voice barge-in in telephony speech recognition</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,270" target="_blank" rel="nofollow">7,437,270</a></td>
	<td valign="top">Performance state management</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,134" target="_blank" rel="nofollow">7,437,134</a></td>
	<td valign="top">Tuner arrangement</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,133" target="_blank" rel="nofollow">7,437,133</a></td>
	<td valign="top">Radio frequency tuner front end and tuner</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,026" target="_blank" rel="nofollow">7,437,026</a></td>
	<td valign="top">Three dimensional semiconductor based optical switching device</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,903" target="_blank" rel="nofollow">7,436,903</a></td>
	<td valign="top">Multicarrier transmitter and method for transmitting multiple data streams with cyclic delay diversity</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,867" target="_blank" rel="nofollow">7,436,867</a></td>
	<td valign="top">Hermetically sealed external cavity laser system and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,846" target="_blank" rel="nofollow">7,436,846</a></td>
	<td valign="top">Network device architecture and associated methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,829" target="_blank" rel="nofollow">7,436,829</a></td>
	<td valign="top">Methods and apparatus for reconfiguring packets to have varying sizes and latencies</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,727" target="_blank" rel="nofollow">7,436,727</a></td>
	<td valign="top">Method and apparatus to control a power consumption of a memory device</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,411" target="_blank" rel="nofollow">7,436,411</a></td>
	<td valign="top">Apparatus and method for rendering a video image as a texture using multiple levels of resolution of the video image</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,277" target="_blank" rel="nofollow">7,436,277</a></td>
	<td valign="top">Power transformer</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,220" target="_blank" rel="nofollow">7,436,220</a></td>
	<td valign="top">Partially gated mux-latch keeper</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,215" target="_blank" rel="nofollow">7,436,215</a></td>
	<td valign="top">Transmitter</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,193" target="_blank" rel="nofollow">7,436,193</a></td>
	<td valign="top">Thin film probe card contact drive system</td>
	</tr>
	<tr>
	<td valign="top" align="right">35</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,058" target="_blank" rel="nofollow">7,436,058</a></td>
	<td valign="top">Reactive solder material</td>
	</tr>
	<tr>
	<td valign="top" align="right">36</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,035" target="_blank" rel="nofollow">7,436,035</a></td>
	<td valign="top">Method of fabricating a field effect transistor structure with abrupt source/drain junctions</td>
	</tr>
	<tr>
	<td valign="top" align="right">37</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,987" target="_blank" rel="nofollow">7,435,987</a></td>
	<td valign="top">Forming a type I heterostructure in a group IV semiconductor</td>
	</tr>
	<tr>
	<td valign="top" align="right">38</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,683" target="_blank" rel="nofollow">7,435,683</a></td>
	<td valign="top">Apparatus and method for selectively recessing spacers on multi-gate devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">39</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,679" target="_blank" rel="nofollow">7,435,679</a></td>
	<td valign="top">Alloyed underlayer for microelectronic interconnects</td>
	</tr>
	<tr>
	<td valign="top" align="right">40</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,675" target="_blank" rel="nofollow">7,435,675</a></td>
	<td valign="top">Method of providing a pre-patterned high-k dielectric film</td>
	</tr>
	<tr>
	<td valign="top" align="right">41</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,664" target="_blank" rel="nofollow">7,435,664</a></td>
	<td valign="top">Wafer-level bonding for mechanically reinforced ultra-thin die</td>
	</tr>
	<tr>
	<td valign="top" align="right">42</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,637" target="_blank" rel="nofollow">7,435,637</a></td>
	<td valign="top">Quantum wire gate device and method of making same</td>
	</tr>
	<tr>
	<td valign="top" align="right">43</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,623" target="_blank" rel="nofollow">7,435,623</a></td>
	<td valign="top">Integrated micro channels and manifold/plenum using separate silicon or low-cost polycrystalline silicon</td>
	</tr>
	<tr>
	<td valign="top" align="right">44</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,306" target="_blank" rel="nofollow">7,434,306</a></td>
	<td valign="top">Integrated transformer</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 09 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/09/intel-patent-applications-published-on-09-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/09/intel-patent-applications-published-on-09-october-2008/#comments</comments>
		<pubDate>Thu, 09 Oct 2008 11:32:28 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/09/intel-patent-applications-published-on-09-october-2008/</guid>
		<description><![CDATA[	2 US patent applications published on 09 October 2008 and assigned to Intel

	
	
	1
	20080250168
	METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS
	
	
	2
	20080250145
	APPARATUS AND COMPUTER-READABLE MEDIA FOR RECOVERABLE WORKFLOW
	
	
]]></description>
			<content:encoded><![CDATA[	<p>2 US patent applications published on 09 October 2008 and assigned to Intel<br />
<a id="more-5024"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080250168.PGNR.&#038;OS=DN/20080250168RS=DN/20080250168" target="_blank">20080250168</a></td>
	<td valign="top">METHOD AND APPARATUS FOR IMPLEMENTING HETEROGENEOUS INTERCONNECTS</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080250145.PGNR.&#038;OS=DN/20080250145RS=DN/20080250145" target="_blank">20080250145</a></td>
	<td valign="top">APPARATUS AND COMPUTER-READABLE MEDIA FOR RECOVERABLE WORKFLOW</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patents granted on 07 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/07/intel-patents-granted-on-07-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/07/intel-patents-granted-on-07-october-2008/#comments</comments>
		<pubDate>Wed, 08 Oct 2008 03:34:18 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/10/07/intel-patents-granted-on-07-october-2008/</guid>
		<description><![CDATA[	33 US patents granted on 07 October 2008 and assigned to Intel

	
	
	1
	7,434,256
	Security management for wireless clients
	
	
	2
	7,434,231
	Methods and apparatus to protect a protocol interface
	
	
	3
	7,434,221
	Multi-threaded sequenced receive for fast network port stream of packets
	
	
	4
	7,434,171
	Performance control apparatus
	
	
	5
	7,434,102
	High density compute center resilient booting
	
	
	6
	7,434,085
	Architecture for high availability using system management mode driven monitoring and communications
	
	
	7
	7,434,073
	Frequency and voltage scaling architecture
	
	
	8
	7,434,068
	Content protection [...]]]></description>
			<content:encoded><![CDATA[	<p>33 US patents granted on 07 October 2008 and assigned to Intel<br />
<a id="more-5004"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,256" target="_blank" rel="nofollow">7,434,256</a></td>
	<td valign="top">Security management for wireless clients</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,231" target="_blank" rel="nofollow">7,434,231</a></td>
	<td valign="top">Methods and apparatus to protect a protocol interface</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,221" target="_blank" rel="nofollow">7,434,221</a></td>
	<td valign="top">Multi-threaded sequenced receive for fast network port stream of packets</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,171" target="_blank" rel="nofollow">7,434,171</a></td>
	<td valign="top">Performance control apparatus</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,102" target="_blank" rel="nofollow">7,434,102</a></td>
	<td valign="top">High density compute center resilient booting</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,085" target="_blank" rel="nofollow">7,434,085</a></td>
	<td valign="top">Architecture for high availability using system management mode driven monitoring and communications</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,073" target="_blank" rel="nofollow">7,434,073</a></td>
	<td valign="top">Frequency and voltage scaling architecture</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,068" target="_blank" rel="nofollow">7,434,068</a></td>
	<td valign="top">Content protection in non-volatile storage devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,028" target="_blank" rel="nofollow">7,434,028</a></td>
	<td valign="top">Hardware stack having entries with a data portion and associated counter</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,006" target="_blank" rel="nofollow">7,434,006</a></td>
	<td valign="top">Non-speculative distributed conflict resolution for a cache coherency protocol</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,992" target="_blank" rel="nofollow">7,433,992</a></td>
	<td valign="top">Command controlling different operations in different chips</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,985" target="_blank" rel="nofollow">7,433,985</a></td>
	<td valign="top">Conditional and vectored system management interrupts</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,975" target="_blank" rel="nofollow">7,433,975</a></td>
	<td valign="top">Integrated circuit capable of marker stripping</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,971" target="_blank" rel="nofollow">7,433,971</a></td>
	<td valign="top">Interface and related methods for dynamic channelization in an ethernet architecture</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,942" target="_blank" rel="nofollow">7,433,942</a></td>
	<td valign="top">Network management</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,603" target="_blank" rel="nofollow">7,433,603</a></td>
	<td valign="top">Using active and passive optical components for an optical network</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,469" target="_blank" rel="nofollow">7,433,469</a></td>
	<td valign="top">Apparatus and method for implementing the KASUMI ciphering process</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,429" target="_blank" rel="nofollow">7,433,429</a></td>
	<td valign="top">De-interleaver method and system</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,383" target="_blank" rel="nofollow">7,433,383</a></td>
	<td valign="top">Techniques to detect radar in a communication signal</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,364" target="_blank" rel="nofollow">7,433,364</a></td>
	<td valign="top">Method for optimizing queuing performance</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,307" target="_blank" rel="nofollow">7,433,307</a></td>
	<td valign="top">Flow control in a network environment</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,937" target="_blank" rel="nofollow">7,432,937</a></td>
	<td valign="top">System and method for concave polygon rasterization</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,876" target="_blank" rel="nofollow">7,432,876</a></td>
	<td valign="top">Display system and method for image copy to a remote display</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,808" target="_blank" rel="nofollow">7,432,808</a></td>
	<td valign="top">Wireless module enabled component carrier for parts inventory and tracking</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,779" target="_blank" rel="nofollow">7,432,779</a></td>
	<td valign="top">Transmission line impedance matching</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,731" target="_blank" rel="nofollow">7,432,731</a></td>
	<td valign="top">Method and apparatus to calibrate DRAM on resistance (Ron) and on-die termination (ODT) values over process, voltage and temperature (PVT) variations</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,592" target="_blank" rel="nofollow">7,432,592</a></td>
	<td valign="top">Integrated micro-channels for 3D through silicon architectures</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,532" target="_blank" rel="nofollow">7,432,532</a></td>
	<td valign="top">Electronic assembly including a die having an integrated circuit and a layer of diamond to transfer heat</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,202" target="_blank" rel="nofollow">7,432,202</a></td>
	<td valign="top">Method of substrate manufacture that decreases the package resistance</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,200" target="_blank" rel="nofollow">7,432,200</a></td>
	<td valign="top">Filling narrow and high aspect ratio openings using electroless deposition</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,113" target="_blank" rel="nofollow">7,432,113</a></td>
	<td valign="top">Surface modification of metals for biomolecule detection using surface enhanced Raman scattering (SERS)</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,112" target="_blank" rel="nofollow">7,432,112</a></td>
	<td valign="top">Surface modification of metals for biomolecule detection using surface enhanced Raman scattering (SERS)</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,870" target="_blank" rel="nofollow">7,430,870</a></td>
	<td valign="top">Localized microelectronic cooling</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Intel patent applications published on 02 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/02/intel-patent-applications-published-on-02-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/02/intel-patent-applications-published-on-02-october-2008/#comments</comments>
		<pubDate>Thu, 02 Oct 2008 11:55:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Intel</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/02/intel-patent-applications-published-on-02-october-2008/</guid>
		<description><![CDATA[	16 US patent applications published on 02 October 2008 and assigned to Intel

	
	
	1
	20080244291
	Resource power controller
	
	
	2
	20080244267
	Local and remote access control of a resource
	
	
	3
	20080244262
	ENHANCED SUPPLICANT FRAMEWORK FOR WIRELESS COMMUNICATIONS
	
	
	4
	20080244222
	MANY-CORE PROCESSING USING VIRTUAL PROCESSORS
	
	
	5
	20080244141
	HIGH BANDWIDTH CABLE EXTENSIONS
	
	
	6
	20080244089
	INTERFACE FOR A DELAY-TOLERANT NETWORK
	
	
	7
	20080244061
	METHOD FOR MANAGING RESOURCES
	
	
	8
	20080243900
	Dynamic and Real-Time Discovery of Computing Resources
	
	
	9
	20080242120
	Right-Angle Coaxial Connector
	
	
	10
	20080240612
	NON-OVERLAP REGION BASED AUTOMATIC GLOBAL ALIGNMENT FOR [...]]]></description>
			<content:encoded><![CDATA[	<p>16 US patent applications published on 02 October 2008 and assigned to Intel<br />
<a id="more-4984"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244291.PGNR.&#038;OS=DN/20080244291RS=DN/20080244291" target="_blank">20080244291</a></td>
	<td valign="top">Resource power controller</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244267.PGNR.&#038;OS=DN/20080244267RS=DN/20080244267" target="_blank">20080244267</a></td>
	<td valign="top">Local and remote access control of a resource</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244262.PGNR.&#038;OS=DN/20080244262RS=DN/20080244262" target="_blank">20080244262</a></td>
	<td valign="top">ENHANCED SUPPLICANT FRAMEWORK FOR WIRELESS COMMUNICATIONS</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244222.PGNR.&#038;OS=DN/20080244222RS=DN/20080244222" target="_blank">20080244222</a></td>
	<td valign="top">MANY-CORE PROCESSING USING VIRTUAL PROCESSORS</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244141.PGNR.&#038;OS=DN/20080244141RS=DN/20080244141" target="_blank">20080244141</a></td>
	<td valign="top">HIGH BANDWIDTH CABLE EXTENSIONS</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244089.PGNR.&#038;OS=DN/20080244089RS=DN/20080244089" target="_blank">20080244089</a></td>
	<td valign="top">INTERFACE FOR A DELAY-TOLERANT NETWORK</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080244061.PGNR.&#038;OS=DN/20080244061RS=DN/20080244061" target="_blank">20080244061</a></td>
	<td valign="top">METHOD FOR MANAGING RESOURCES</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080243900.PGNR.&#038;OS=DN/20080243900RS=DN/20080243900" target="_blank">20080243900</a></td>
	<td valign="top">Dynamic and Real-Time Discovery of Computing Resources</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080242120.PGNR.&#038;OS=DN/20080242120RS=DN/20080242120" target="_blank">20080242120</a></td>
	<td valign="top">Right-Angle Coaxial Connector</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080240612.PGNR.&#038;OS=DN/20080240612RS=DN/20080240612" target="_blank">20080240612</a></td>
	<td valign="top">NON-OVERLAP REGION BASED AUTOMATIC GLOBAL ALIGNMENT FOR RING CAMERA IMAGE MOSAIC</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080240313.PGNR.&#038;OS=DN/20080240313RS=DN/20080240313" target="_blank">20080240313</a></td>
	<td valign="top">Closed Loop Adaptive Clock RFI Mitigation</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080240218.PGNR.&#038;OS=DN/20080240218RS=DN/20080240218" target="_blank">20080240218</a></td>
	<td valign="top">Automatic calibration circuit for a continuous-time equalizer</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080239772.PGNR.&#038;OS=DN/20080239772RS=DN/20080239772" target="_blank">20080239772</a></td>
	<td valign="top">SWITCHED CAPACITOR CONVERTERS</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080238407.PGNR.&#038;OS=DN/20080238407RS=DN/20080238407" target="_blank">20080238407</a></td>
	<td valign="top">PACKAGE LEVEL VOLTAGE SENSING OF A POWER GATED DIE</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080238380.PGNR.&#038;OS=DN/20080238380RS=DN/20080238380" target="_blank">20080238380</a></td>
	<td valign="top">HIERARCHICAL CONTROL FOR AN INTEGRATED VOLTAGE REGULATOR</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080236871.PGNR.&#038;OS=DN/20080236871RS=DN/20080236871" target="_blank">20080236871</a></td>
	<td valign="top">Gas Venting Component Mounting Pad</td>
	</tr>
	</table>
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		]]></content:encoded>
			<wfw:commentRSS>http://www.latestpatents.com/2008/10/02/intel-patent-applications-published-on-02-october-2008/feed/</wfw:commentRSS>
	</item>
		<item>
		<title>Intel patents granted on 30 September 2008</title>
		<link>http://www.latestpatents.com/2008/09/30/intel-patents-granted-on-30-september-2008/</link>
		<comments>http://www.latestpatents.com/2008/09/30/intel-patents-granted-on-30-september-2008/#comments</comments>
		<pubDate>Tue, 30 Sep 2008 13:29:57 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Intel</category>
		<guid>http://www.latestpatents.com/2008/09/30/intel-patents-granted-on-30-september-2008/</guid>
		<description><![CDATA[	19 US patents granted on 30 September 2008 and assigned to Intel

	
	
	1
	7,430,683
	Method and apparatus for enabling run-time recovery of a failed platform
	
	
	2
	7,430,673
	Power management system for computing platform
	
	
	3
	7,430,672
	Method and apparatus to monitor power consumption of processor
	
	
	4
	7,430,657
	System, method and device for queuing branch predictions
	
	
	5
	7,430,656
	System and method of converting data formats and communicating between execution units
	
	
	6
	7,430,578
	Method and apparatus [...]]]></description>
			<content:encoded><![CDATA[	<p>19 US patents granted on 30 September 2008 and assigned to Intel<br />
<a id="more-4964"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,683" target="_blank" rel="nofollow">7,430,683</a></td>
	<td valign="top">Method and apparatus for enabling run-time recovery of a failed platform</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,673" target="_blank" rel="nofollow">7,430,673</a></td>
	<td valign="top">Power management system for computing platform</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,672" target="_blank" rel="nofollow">7,430,672</a></td>
	<td valign="top">Method and apparatus to monitor power consumption of processor</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,657" target="_blank" rel="nofollow">7,430,657</a></td>
	<td valign="top">System, method and device for queuing branch predictions</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,656" target="_blank" rel="nofollow">7,430,656</a></td>
	<td valign="top">System and method of converting data formats and communicating between execution units</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,578" target="_blank" rel="nofollow">7,430,578</a></td>
	<td valign="top">Method and apparatus for performing multiply-add operations on packed byte data</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,574" target="_blank" rel="nofollow">7,430,574</a></td>
	<td valign="top">Efficient execution and emulation of bit scan operations</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,419" target="_blank" rel="nofollow">7,430,419</a></td>
	<td valign="top">Rapid decoding of control channel to decrease handoff time</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,411" target="_blank" rel="nofollow">7,430,411</a></td>
	<td valign="top">Transmission of service availability information</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,252" target="_blank" rel="nofollow">7,430,252</a></td>
	<td valign="top">Apparatus and method for WGIO phase modulation</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,119" target="_blank" rel="nofollow">7,430,119</a></td>
	<td valign="top">Impeller and align