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	<title>Latest Patents &#187; Micron</title>
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		<title>Micron patent applications published on 02 September 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-02-september-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-02-september-2010/#comments</comments>
		<pubDate>Thu, 02 Sep 2010 13:42:53 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10350</guid>
		<description><![CDATA[11 US patent applications published on 02 September 2010 and assigned to Micron



1
20100223512
SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT IN SELF TESTING USING MICROCODE SEQUENCERS


2
20100223406
MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS


3
20100222913
METHODS FOR NON LOT-BASED INTEGRATED CIRCUIT MANUFACTURING


4
20100221920
SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES


5
20100221916
Methods of Etching Oxide, Reducing Roughness, and Forming Capacitor [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patent applications published on 02 September 2010 and assigned to Micron<br />
<span id="more-10350"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100223512.PGNR.&#038;OS=DN/20100223512RS=DN/20100223512" target="_blank">20100223512</a></td>
<td valign="top">SYSTEM, APPARATUS, AND METHOD FOR MEMORY BUILT IN SELF TESTING USING MICROCODE SEQUENCERS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100223406.PGNR.&#038;OS=DN/20100223406RS=DN/20100223406" target="_blank">20100223406</a></td>
<td valign="top">MEMORY MODULES HAVING DAISY CHAIN WIRING CONFIGURATIONS AND FILTERS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100222913.PGNR.&#038;OS=DN/20100222913RS=DN/20100222913" target="_blank">20100222913</a></td>
<td valign="top">METHODS FOR NON LOT-BASED INTEGRATED CIRCUIT MANUFACTURING</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100221920.PGNR.&#038;OS=DN/20100221920RS=DN/20100221920" target="_blank">20100221920</a></td>
<td valign="top">SPACER PROCESS FOR ON PITCH CONTACTS AND RELATED STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100221916.PGNR.&#038;OS=DN/20100221916RS=DN/20100221916" target="_blank">20100221916</a></td>
<td valign="top">Methods of Etching Oxide, Reducing Roughness, and Forming Capacitor Constructions</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100220530.PGNR.&#038;OS=DN/20100220530RS=DN/20100220530" target="_blank">20100220530</a></td>
<td valign="top">CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100220528.PGNR.&#038;OS=DN/20100220528RS=DN/20100220528" target="_blank">20100220528</a></td>
<td valign="top">NAND WITH BACK BIASED OPERATION</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100219520.PGNR.&#038;OS=DN/20100219520RS=DN/20100219520" target="_blank">20100219520</a></td>
<td valign="top">LEAD FRAME</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100219515.PGNR.&#038;OS=DN/20100219515RS=DN/20100219515" target="_blank">20100219515</a></td>
<td valign="top">LEAD FRAME</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100219501.PGNR.&#038;OS=DN/20100219501RS=DN/20100219501" target="_blank">20100219501</a></td>
<td valign="top">TRENCH ISOLATION IMPLANTATION</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100219421.PGNR.&#038;OS=DN/20100219421RS=DN/20100219421" target="_blank">20100219421</a></td>
<td valign="top">METHOD AND SYSTEM FOR ELECTRICALLY COUPLING A CHIP TO CHIP PACKAGE</td>
</tr>
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]]></content:encoded>
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		</item>
		<item>
		<title>Micron patents granted on 31 August 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-31-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-31-august-2010/#comments</comments>
		<pubDate>Tue, 31 Aug 2010 16:06:10 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10308</guid>
		<description><![CDATA[14 US patents granted on 31 August 2010 and assigned to Micron



1
7,788,451
Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system


2
7,787,310
Circuits, devices, systems, and methods of operation for capturing data signals


3
7,787,307
Memory cell shift estimation method and apparatus


4
7,787,282
Sensing resistance variable memory


5
7,786,803
Operational transconductance amplifier (OTA)


6
7,786,605
Stacked semiconductor components with through wire interconnects [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patents granted on 31 August 2010 and assigned to Micron<br />
<span id="more-10308"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,788,451" target="_blank" rel="nofollow">7,788,451</a></td>
<td valign="top">Apparatus and method for data bypass for a bi-directional data bus in a hub-based memory sub-system</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,310" target="_blank" rel="nofollow">7,787,310</a></td>
<td valign="top">Circuits, devices, systems, and methods of operation for capturing data signals</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,307" target="_blank" rel="nofollow">7,787,307</a></td>
<td valign="top">Memory cell shift estimation method and apparatus</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,787,282" target="_blank" rel="nofollow">7,787,282</a></td>
<td valign="top">Sensing resistance variable memory</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,803" target="_blank" rel="nofollow">7,786,803</a></td>
<td valign="top">Operational transconductance amplifier (OTA)</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,605" target="_blank" rel="nofollow">7,786,605</a></td>
<td valign="top">Stacked semiconductor components with through wire interconnects (TWI)</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,522" target="_blank" rel="nofollow">7,786,522</a></td>
<td valign="top">Method for forming memory cell and device</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,516" target="_blank" rel="nofollow">7,786,516</a></td>
<td valign="top">Discrete trap non-volatile multi-functional memory device</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,786,016" target="_blank" rel="nofollow">7,786,016</a></td>
<td valign="top">Methods of uniformly removing silicon oxide and a method of removing a sacrificial oxide</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,998" target="_blank" rel="nofollow">7,785,998</a></td>
<td valign="top">Methods of forming dispersions of nanoparticles, and methods of forming flash memory cells</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,978" target="_blank" rel="nofollow">7,785,978</a></td>
<td valign="top">Method of forming memory cell using gas cluster ion beams</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,976" target="_blank" rel="nofollow">7,785,976</a></td>
<td valign="top">Method of forming a memory device incorporating a resistance-variable chalcogenide element</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,962" target="_blank" rel="nofollow">7,785,962</a></td>
<td valign="top">Methods of forming a plurality of capacitors</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,785,961" target="_blank" rel="nofollow">7,785,961</a></td>
<td valign="top">Trench DRAM cell with vertical device and buried word lines</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patent applications published on 26 August 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-26-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-26-august-2010/#comments</comments>
		<pubDate>Thu, 26 Aug 2010 14:31:47 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10268</guid>
		<description><![CDATA[9 US patent applications published on 26 August 2010 and assigned to Micron



1
20100216307
SIMPLIFIED PITCH DOUBLING PROCESS FLOW


2
20100216297
METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES


3
20100214864
MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME


4
20100214855
METHODS OF QUANTIZING SIGNALS USING VARIABLE REFERENCE SIGNALS


5
20100214821
CAPACITIVE DIVIDER SENSING OF MEMORY CELLS


6
20100213972
DEVICES AND METHODS FOR DRIVING A SIGNAL OFF AN INTEGRATED [...]]]></description>
			<content:encoded><![CDATA[<p>9 US patent applications published on 26 August 2010 and assigned to Micron<br />
<span id="more-10268"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100216307.PGNR.&#038;OS=DN/20100216307RS=DN/20100216307" target="_blank">20100216307</a></td>
<td valign="top">SIMPLIFIED PITCH DOUBLING PROCESS FLOW</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100216297.PGNR.&#038;OS=DN/20100216297RS=DN/20100216297" target="_blank">20100216297</a></td>
<td valign="top">METHODS FOR FABRICATING SEMICONDUCTOR DEVICE STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100214864.PGNR.&#038;OS=DN/20100214864RS=DN/20100214864" target="_blank">20100214864</a></td>
<td valign="top">MEMORY DEVICE COMMAND DECODING SYSTEM AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100214855.PGNR.&#038;OS=DN/20100214855RS=DN/20100214855" target="_blank">20100214855</a></td>
<td valign="top">METHODS OF QUANTIZING SIGNALS USING VARIABLE REFERENCE SIGNALS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100214821.PGNR.&#038;OS=DN/20100214821RS=DN/20100214821" target="_blank">20100214821</a></td>
<td valign="top">CAPACITIVE DIVIDER SENSING OF MEMORY CELLS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100213972.PGNR.&#038;OS=DN/20100213972RS=DN/20100213972" target="_blank">20100213972</a></td>
<td valign="top">DEVICES AND METHODS FOR DRIVING A SIGNAL OFF AN INTEGRATED CIRCUIT</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100213578.PGNR.&#038;OS=DN/20100213578RS=DN/20100213578" target="_blank">20100213578</a></td>
<td valign="top">METHODS OF FORMING INTEGRATED CIRCUITS AND RESULTING STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100213574.PGNR.&#038;OS=DN/20100213574RS=DN/20100213574" target="_blank">20100213574</a></td>
<td valign="top">HIGH DIELECTRIC CONSTANT TRANSITION METAL OXIDE MATERIALS</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100213458.PGNR.&#038;OS=DN/20100213458RS=DN/20100213458" target="_blank">20100213458</a></td>
<td valign="top">RIGID SEMICONDUCTOR MEMORY HAVING AMORPHOUS METAL OXIDE SEMICONDUCTOR CHANNELS</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 24 August 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-24-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-24-august-2010/#comments</comments>
		<pubDate>Tue, 24 Aug 2010 13:12:08 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10228</guid>
		<description><![CDATA[8 US patents granted on 24 August 2010 and assigned to Micron



1
7,783,934
Program failure recovery


2
7,782,677
NAND memory device column charging


3
7,782,674
Sensing of memory cells in NAND flash


4
7,781,877
Packaged integrated circuit devices with through-body conductive vias, and methods of making same


5
7,781,875
Techniques for packaging multiple device components


6
7,781,868
Semiconductor components having through interconnects and backside redistribution conductors


7
7,781,860
Semiconductor constructions, and electronic systems


8
7,781,818
Semiconductor constructions containing [...]]]></description>
			<content:encoded><![CDATA[<p>8 US patents granted on 24 August 2010 and assigned to Micron<br />
<span id="more-10228"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,783,934" target="_blank" rel="nofollow">7,783,934</a></td>
<td valign="top">Program failure recovery</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,677" target="_blank" rel="nofollow">7,782,677</a></td>
<td valign="top">NAND memory device column charging</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,782,674" target="_blank" rel="nofollow">7,782,674</a></td>
<td valign="top">Sensing of memory cells in NAND flash</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,877" target="_blank" rel="nofollow">7,781,877</a></td>
<td valign="top">Packaged integrated circuit devices with through-body conductive vias, and methods of making same</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,875" target="_blank" rel="nofollow">7,781,875</a></td>
<td valign="top">Techniques for packaging multiple device components</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,868" target="_blank" rel="nofollow">7,781,868</a></td>
<td valign="top">Semiconductor components having through interconnects and backside redistribution conductors</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,860" target="_blank" rel="nofollow">7,781,860</a></td>
<td valign="top">Semiconductor constructions, and electronic systems</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,781,818" target="_blank" rel="nofollow">7,781,818</a></td>
<td valign="top">Semiconductor constructions containing tubular capacitor storage nodes, and retaining structures along portions of the tubular capacitor storage nodes</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 19 August 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-19-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-19-august-2010/#comments</comments>
		<pubDate>Thu, 19 Aug 2010 14:24:21 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10189</guid>
		<description><![CDATA[7 US patent applications published on 19 August 2010 and assigned to Micron



1
20100211834
DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS


2
20100211745
MEMORY PREFETCH SYSTEMS AND METHODS


3
20100211733
DATA VALID INDICATION METHOD AND APPARATUS


4
20100211721
MEMORY NETWORK METHODS, APPARATUS, AND SYSTEMS


5
20100208533
SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY


6
20100208524
SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE


7
20100208523
DYNAMIC SOFT PROGRAM TRIMS


]]></description>
			<content:encoded><![CDATA[<p>7 US patent applications published on 19 August 2010 and assigned to Micron<br />
<span id="more-10189"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100211834.PGNR.&#038;OS=DN/20100211834RS=DN/20100211834" target="_blank">20100211834</a></td>
<td valign="top">DATA INTEGRITY IN MEMORY CONTROLLERS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100211745.PGNR.&#038;OS=DN/20100211745RS=DN/20100211745" target="_blank">20100211745</a></td>
<td valign="top">MEMORY PREFETCH SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100211733.PGNR.&#038;OS=DN/20100211733RS=DN/20100211733" target="_blank">20100211733</a></td>
<td valign="top">DATA VALID INDICATION METHOD AND APPARATUS</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100211721.PGNR.&#038;OS=DN/20100211721RS=DN/20100211721" target="_blank">20100211721</a></td>
<td valign="top">MEMORY NETWORK METHODS, APPARATUS, AND SYSTEMS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100208533.PGNR.&#038;OS=DN/20100208533RS=DN/20100208533" target="_blank">20100208533</a></td>
<td valign="top">SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100208524.PGNR.&#038;OS=DN/20100208524RS=DN/20100208524" target="_blank">20100208524</a></td>
<td valign="top">SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100208523.PGNR.&#038;OS=DN/20100208523RS=DN/20100208523" target="_blank">20100208523</a></td>
<td valign="top">DYNAMIC SOFT PROGRAM TRIMS</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 17 August 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-17-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-17-august-2010/#comments</comments>
		<pubDate>Tue, 17 Aug 2010 13:50:53 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10149</guid>
		<description><![CDATA[16 US patents granted on 17 August 2010 and assigned to Micron



1
7,779,212
Method and apparatus for sending data from multiple sources over a communications bus


2
7,778,812
Selecting data to verify in hardware device model simulation test generation


3
7,778,092
Memory system and method having volatile and non-volatile memory devices at same hierarchical level


4
7,778,086
Erase operation control sequencing apparatus, systems, and methods


5
7,778,039
Substrates, systems, [...]]]></description>
			<content:encoded><![CDATA[<p>16 US patents granted on 17 August 2010 and assigned to Micron<br />
<span id="more-10149"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,779,212" target="_blank" rel="nofollow">7,779,212</a></td>
<td valign="top">Method and apparatus for sending data from multiple sources over a communications bus</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,812" target="_blank" rel="nofollow">7,778,812</a></td>
<td valign="top">Selecting data to verify in hardware device model simulation test generation</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,092" target="_blank" rel="nofollow">7,778,092</a></td>
<td valign="top">Memory system and method having volatile and non-volatile memory devices at same hierarchical level</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,086" target="_blank" rel="nofollow">7,778,086</a></td>
<td valign="top">Erase operation control sequencing apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,778,039" target="_blank" rel="nofollow">7,778,039</a></td>
<td valign="top">Substrates, systems, and devices including structures for suppressing power and ground plane noise, and methods for suppressing power and ground plane noise</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,777,287" target="_blank" rel="nofollow">7,777,287</a></td>
<td valign="top">System and apparatus providing analytical device based on solid state image sensor</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,777,264" target="_blank" rel="nofollow">7,777,264</a></td>
<td valign="top">Random access memory device utilizing a vertically oriented select transistor</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,765" target="_blank" rel="nofollow">7,776,765</a></td>
<td valign="top">Tantalum silicon oxynitride high-k dielectrics and metal gates</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,762" target="_blank" rel="nofollow">7,776,762</a></td>
<td valign="top">Zirconium-doped tantalum oxide films</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,749" target="_blank" rel="nofollow">7,776,749</a></td>
<td valign="top">Methods of forming semiconductor constructions</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,744" target="_blank" rel="nofollow">7,776,744</a></td>
<td valign="top">Pitch multiplication spacers and methods of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,715" target="_blank" rel="nofollow">7,776,715</a></td>
<td valign="top">Reverse construction memory cell</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,683" target="_blank" rel="nofollow">7,776,683</a></td>
<td valign="top">Integrated circuit fabrication</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,652" target="_blank" rel="nofollow">7,776,652</a></td>
<td valign="top">Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,776,647" target="_blank" rel="nofollow">7,776,647</a></td>
<td valign="top">Semiconductor components and methods of fabrication with circuit side contacts, conductive vias and backside conductors</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,775,710" target="_blank" rel="nofollow">7,775,710</a></td>
<td valign="top">DRAM temperature management system</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patent applications published on 12 August 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-12-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-12-august-2010/#comments</comments>
		<pubDate>Thu, 12 Aug 2010 12:34:11 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10107</guid>
		<description><![CDATA[13 US patent applications published on 12 August 2010 and assigned to Micron



1
20100205490
INPUT/OUTPUT COMPRESSION AND PIN REDUCTION IN AN INTEGRATED CIRCUIT


2
20100205489
JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING


3
20100204402
Zwitterionic Block Copolymers And Methods


4
20100203727
METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION


5
20100203719
Method of Forming an Antifuse and a Conductive Interconnect, and Methods of Forming DRAM Circuitry


6
20100202214
VERIFYING AN ERASE THRESHOLD IN A [...]]]></description>
			<content:encoded><![CDATA[<p>13 US patent applications published on 12 August 2010 and assigned to Micron<br />
<span id="more-10107"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100205490.PGNR.&#038;OS=DN/20100205490RS=DN/20100205490" target="_blank">20100205490</a></td>
<td valign="top">INPUT/OUTPUT COMPRESSION AND PIN REDUCTION IN AN INTEGRATED CIRCUIT</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100205489.PGNR.&#038;OS=DN/20100205489RS=DN/20100205489" target="_blank">20100205489</a></td>
<td valign="top">JTAG CONTROLLED SELF-REPAIR AFTER PACKAGING</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100204402.PGNR.&#038;OS=DN/20100204402RS=DN/20100204402" target="_blank">20100204402</a></td>
<td valign="top">Zwitterionic Block Copolymers And Methods</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100203727.PGNR.&#038;OS=DN/20100203727RS=DN/20100203727" target="_blank">20100203727</a></td>
<td valign="top">METHOD FOR INTEGRATED CIRCUIT FABRICATION USING PITCH MULTIPLICATION</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100203719.PGNR.&#038;OS=DN/20100203719RS=DN/20100203719" target="_blank">20100203719</a></td>
<td valign="top">Method of Forming an Antifuse and a Conductive Interconnect, and Methods of Forming DRAM Circuitry</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202214.PGNR.&#038;OS=DN/20100202214RS=DN/20100202214" target="_blank">20100202214</a></td>
<td valign="top">VERIFYING AN ERASE THRESHOLD IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202210.PGNR.&#038;OS=DN/20100202210RS=DN/20100202210" target="_blank">20100202210</a></td>
<td valign="top">REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202202.PGNR.&#038;OS=DN/20100202202RS=DN/20100202202" target="_blank">20100202202</a></td>
<td valign="top">ADJUSTING FOR CHARGE LOSS IN A MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202201.PGNR.&#038;OS=DN/20100202201RS=DN/20100202201" target="_blank">20100202201</a></td>
<td valign="top">MEMORY ARRAY WITH INVERTED DATA-LINE PAIRS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100202195.PGNR.&#038;OS=DN/20100202195RS=DN/20100202195" target="_blank">20100202195</a></td>
<td valign="top">PHASE CHANGE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100201415.PGNR.&#038;OS=DN/20100201415RS=DN/20100201415" target="_blank">20100201415</a></td>
<td valign="top">METHOD AND APPARATUS FOR OUTPUT DATA SYNCHRONIZATION WITH SYSTEM CLOCK</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100200836.PGNR.&#038;OS=DN/20100200836RS=DN/20100200836" target="_blank">20100200836</a></td>
<td valign="top">NANOPARTICLE POSITIONING TECHNIQUE</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100200830.PGNR.&#038;OS=DN/20100200830RS=DN/20100200830" target="_blank">20100200830</a></td>
<td valign="top">MEMORY DEVICE HAVING SELF-ALIGNED CELL STRUCTURE</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 10 August 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-10-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-10-august-2010/#comments</comments>
		<pubDate>Tue, 10 Aug 2010 13:44:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10069</guid>
		<description><![CDATA[21 US patents granted on 10 August 2010 and assigned to Micron



1
7,774,683
Erasure pointer error correction


2
7,774,559
Method and system for terminating write commands in a hub-based memory system


3
7,774,536
Power up initialization for memory


4
7,773,492
Method and apparatus providing high density data storage


5
7,773,441
Memory malfunction prediction system and method


6
7,773,418
Non-volatile memory with both single and multiple level cells


7
7,773,412
Method and apparatus for providing a [...]]]></description>
			<content:encoded><![CDATA[<p>21 US patents granted on 10 August 2010 and assigned to Micron<br />
<span id="more-10069"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,683" target="_blank" rel="nofollow">7,774,683</a></td>
<td valign="top">Erasure pointer error correction</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,559" target="_blank" rel="nofollow">7,774,559</a></td>
<td valign="top">Method and system for terminating write commands in a hub-based memory system</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,774,536" target="_blank" rel="nofollow">7,774,536</a></td>
<td valign="top">Power up initialization for memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,492" target="_blank" rel="nofollow">7,773,492</a></td>
<td valign="top">Method and apparatus providing high density data storage</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,441" target="_blank" rel="nofollow">7,773,441</a></td>
<td valign="top">Memory malfunction prediction system and method</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,418" target="_blank" rel="nofollow">7,773,418</a></td>
<td valign="top">Non-volatile memory with both single and multiple level cells</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,773,412" target="_blank" rel="nofollow">7,773,412</a></td>
<td valign="top">Method and apparatus for providing a non-volatile memory with reduced cell capacitive coupling</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,908" target="_blank" rel="nofollow">7,772,908</a></td>
<td valign="top">Voltage and temperature compensation delay system and method</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,680" target="_blank" rel="nofollow">7,772,680</a></td>
<td valign="top">Arrangements of fuse-type constructions</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,672" target="_blank" rel="nofollow">7,772,672</a></td>
<td valign="top">Semiconductor constructions</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,635" target="_blank" rel="nofollow">7,772,635</a></td>
<td valign="top">Non-volatile memory device with tensile strained silicon layer</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,633" target="_blank" rel="nofollow">7,772,633</a></td>
<td valign="top">DRAM cells with vertical transistors</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,632" target="_blank" rel="nofollow">7,772,632</a></td>
<td valign="top">Memory arrays and methods of fabricating memory arrays</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,583" target="_blank" rel="nofollow">7,772,583</a></td>
<td valign="top">Memory devices and methods of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,537" target="_blank" rel="nofollow">7,772,537</a></td>
<td valign="top">Linear distributed pixel differential amplifier having mirrored inputs</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,116" target="_blank" rel="nofollow">7,772,116</a></td>
<td valign="top">Methods of forming blind wafer interconnects</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,115" target="_blank" rel="nofollow">7,772,115</a></td>
<td valign="top">Methods for forming through-wafer interconnects, intermediate structures so formed, and devices and systems having at least one solder dam structure</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,772,066" target="_blank" rel="nofollow">7,772,066</a></td>
<td valign="top">DRAM tunneling access transistor</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,771,917" target="_blank" rel="nofollow">7,771,917</a></td>
<td valign="top">Methods of making templates for use in imprint lithography</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,771,537" target="_blank" rel="nofollow">7,771,537</a></td>
<td valign="top">Methods and systems for controlling temperature during microfeature workpiece processing, E.G. CVD deposition</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,771,115" target="_blank" rel="nofollow">7,771,115</a></td>
<td valign="top">Temperature sensor circuit, device, system, and method</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patent applications published on 05 August 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-05-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-05-august-2010/#comments</comments>
		<pubDate>Thu, 05 Aug 2010 13:39:55 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=10029</guid>
		<description><![CDATA[18 US patent applications published on 05 August 2010 and assigned to Micron



1
20100199134
DETERMINING SECTOR STATUS IN A MEMORY DEVICE


2
20100199125
Systems and Methods for Storing and Recovering Controller Data in Non-Volatile Memory Devices


3
20100199117
TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER


4
20100199034
METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM


5
20100199019
LOGICAL MEMORY BLOCKS


6
20100199017
Data Encoding Using Spare [...]]]></description>
			<content:encoded><![CDATA[<p>18 US patent applications published on 05 August 2010 and assigned to Micron<br />
<span id="more-10029"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199134.PGNR.&#038;OS=DN/20100199134RS=DN/20100199134" target="_blank">20100199134</a></td>
<td valign="top">DETERMINING SECTOR STATUS IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199125.PGNR.&#038;OS=DN/20100199125RS=DN/20100199125" target="_blank">20100199125</a></td>
<td valign="top">Systems and Methods for Storing and Recovering Controller Data in Non-Volatile Memory Devices</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199117.PGNR.&#038;OS=DN/20100199117RS=DN/20100199117" target="_blank">20100199117</a></td>
<td valign="top">TIMING SYNCHRONIZATION CIRCUIT WITH LOOP COUNTER</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199034.PGNR.&#038;OS=DN/20100199034RS=DN/20100199034" target="_blank">20100199034</a></td>
<td valign="top">METHOD AND APPARATUS FOR ADDRESS FIFO FOR HIGH BANDWIDTH COMMAND/ADDRESS BUSSES IN DIGITAL STORAGE SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199019.PGNR.&#038;OS=DN/20100199019RS=DN/20100199019" target="_blank">20100199019</a></td>
<td valign="top">LOGICAL MEMORY BLOCKS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100199017.PGNR.&#038;OS=DN/20100199017RS=DN/20100199017" target="_blank">20100199017</a></td>
<td valign="top">Data Encoding Using Spare Channels in a Memory System</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100198575.PGNR.&#038;OS=DN/20100198575RS=DN/20100198575" target="_blank">20100198575</a></td>
<td valign="top">Generation and Manipulation of Realistic Signals for Circuit and System Verification</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100197204.PGNR.&#038;OS=DN/20100197204RS=DN/20100197204" target="_blank">20100197204</a></td>
<td valign="top">APPARATUSES AND METHODS FOR CONDITIONING POLISHING PADS USED IN POLISHING MICRO-DEVICE WORKPIECES</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100197131.PGNR.&#038;OS=DN/20100197131RS=DN/20100197131" target="_blank">20100197131</a></td>
<td valign="top">THICKENED SIDEWALL DIELECTRIC FOR MEMORY CELL</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100196807.PGNR.&#038;OS=DN/20100196807RS=DN/20100196807" target="_blank">20100196807</a></td>
<td valign="top">PREVENTION OF PHOTORESIST SCUMMING</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100195421.PGNR.&#038;OS=DN/20100195421RS=DN/20100195421" target="_blank">20100195421</a></td>
<td valign="top">STACKED-DIE MEMORY SYSTEMS AND METHODS FOR TRAINING STACKED-DIE MEMORY SYSTEMS</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100195403.PGNR.&#038;OS=DN/20100195403RS=DN/20100195403" target="_blank">20100195403</a></td>
<td valign="top">ERASE VERIFY IN MEMORY DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100195399.PGNR.&#038;OS=DN/20100195399RS=DN/20100195399" target="_blank">20100195399</a></td>
<td valign="top">MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100195392.PGNR.&#038;OS=DN/20100195392RS=DN/20100195392" target="_blank">20100195392</a></td>
<td valign="top">CAPACITOR STRUCTURE HAVING IMPROVED AREA EFFICIENCY, A MEMORY DEVICE INCLUDING THE SAME, AND A METHOD OF FORMING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100193917.PGNR.&#038;OS=DN/20100193917RS=DN/20100193917" target="_blank">20100193917</a></td>
<td valign="top">METHODS OF ISOLATING ARRAY FEATURES DURING PITCH DOUBLING PROCESSES AND SEMICONDUCTOR DEVICE STRUCTURES HAVING ISOLATED ARRAY FEATURES</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100193897.PGNR.&#038;OS=DN/20100193897RS=DN/20100193897" target="_blank">20100193897</a></td>
<td valign="top">SEMICONDUCTOR MATERIAL MANUFACTURE</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100193853.PGNR.&#038;OS=DN/20100193853RS=DN/20100193853" target="_blank">20100193853</a></td>
<td valign="top">SEMICONDUCTOR DEVICES AND STRUCTURES INCLUDING AT LEAST PARTIALLY FORMED CONTAINER CAPACITORS AND METHODS OF FORMING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100193032.PGNR.&#038;OS=DN/20100193032RS=DN/20100193032" target="_blank">20100193032</a></td>
<td valign="top">Solar Cell Systems</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patents granted on 03 August 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-03-august-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-03-august-2010/#comments</comments>
		<pubDate>Tue, 03 Aug 2010 14:05:45 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9989</guid>
		<description><![CDATA[28 US patents granted on 03 August 2010 and assigned to Micron



1
7,770,079
Error scanning in flash memory


2
7,769,286
Method and apparatus of determining the best focus position of a lens


3
7,768,868
Digital filters for semiconductor devices


4
7,768,861
Software refreshed memory device and method


5
7,768,846
Individual I/O modulation in memory devices


6
7,768,839
Memory read methods, apparatus, and systems


7
7,768,838
Operating memory cells


8
7,768,835
Non-volatile memory erase verify


9
7,768,832
Analog read and write paths [...]]]></description>
			<content:encoded><![CDATA[<p>28 US patents granted on 03 August 2010 and assigned to Micron<br />
<span id="more-9989"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,770,079" target="_blank" rel="nofollow">7,770,079</a></td>
<td valign="top">Error scanning in flash memory</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,769,286" target="_blank" rel="nofollow">7,769,286</a></td>
<td valign="top">Method and apparatus of determining the best focus position of a lens</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,868" target="_blank" rel="nofollow">7,768,868</a></td>
<td valign="top">Digital filters for semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,861" target="_blank" rel="nofollow">7,768,861</a></td>
<td valign="top">Software refreshed memory device and method</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,846" target="_blank" rel="nofollow">7,768,846</a></td>
<td valign="top">Individual I/O modulation in memory devices</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,839" target="_blank" rel="nofollow">7,768,839</a></td>
<td valign="top">Memory read methods, apparatus, and systems</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,838" target="_blank" rel="nofollow">7,768,838</a></td>
<td valign="top">Operating memory cells</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,835" target="_blank" rel="nofollow">7,768,835</a></td>
<td valign="top">Non-volatile memory erase verify</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,832" target="_blank" rel="nofollow">7,768,832</a></td>
<td valign="top">Analog read and write paths in a solid state memory device</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,812" target="_blank" rel="nofollow">7,768,812</a></td>
<td valign="top">Memory cells, memory cell programming methods, memory cell reading methods, memory cell operating methods, and memory devices</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,562" target="_blank" rel="nofollow">7,768,562</a></td>
<td valign="top">Method, apparatus and system providing imager vertical binning and scaling using column parallel sigma-delta digital conversion</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,096" target="_blank" rel="nofollow">7,768,096</a></td>
<td valign="top">System for fabricating semiconductor components with conductive interconnects</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,073" target="_blank" rel="nofollow">7,768,073</a></td>
<td valign="top">Memory array buried digit line</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,062" target="_blank" rel="nofollow">7,768,062</a></td>
<td valign="top">Combined volatile and non-volatile memory device with graded composition insulator stack</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,058" target="_blank" rel="nofollow">7,768,058</a></td>
<td valign="top">NROM flash memory devices on ultrathin silicon</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,051" target="_blank" rel="nofollow">7,768,051</a></td>
<td valign="top">DRAM including a vertical surround gate transistor</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,049" target="_blank" rel="nofollow">7,768,049</a></td>
<td valign="top">Polymer-based ferroelectric memory</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,047" target="_blank" rel="nofollow">7,768,047</a></td>
<td valign="top">Imager element, device and system with recessed transfer gate</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,040" target="_blank" rel="nofollow">7,768,040</a></td>
<td valign="top">Imager device with electric connections to electrical device</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,768,036" target="_blank" rel="nofollow">7,768,036</a></td>
<td valign="top">Integrated circuitry</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,913" target="_blank" rel="nofollow">7,767,913</a></td>
<td valign="top">Electronic devices including conductive vias having two or more conductive elements for providing electrical communication between traces in different planes in a substrate, and accompanying methods</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,557" target="_blank" rel="nofollow">7,767,557</a></td>
<td valign="top">Chilled wafer dicing</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,544" target="_blank" rel="nofollow">7,767,544</a></td>
<td valign="top">Semiconductor fabrication method and system</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,525" target="_blank" rel="nofollow">7,767,525</a></td>
<td valign="top">Methods of forming vertical transistor structures</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,514" target="_blank" rel="nofollow">7,767,514</a></td>
<td valign="top">Methods of implanting dopant into channel regions</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,365" target="_blank" rel="nofollow">7,767,365</a></td>
<td valign="top">Methods for forming and cleaning photolithography reticles</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,363" target="_blank" rel="nofollow">7,767,363</a></td>
<td valign="top">Methods for photo-processing photo-imageable material</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,767,129" target="_blank" rel="nofollow">7,767,129</a></td>
<td valign="top">Imprint templates for imprint lithography, and methods of patterning a plurality of substrates</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 29 July 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-29-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-29-july-2010/#comments</comments>
		<pubDate>Thu, 29 Jul 2010 14:42:06 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9949</guid>
		<description><![CDATA[15 US patent applications published on 29 July 2010 and assigned to Micron



1
20100192041
MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS


2
20100191999
MEMORY DEVICE POWER MANAGERS AND METHODS


3
20100191874
HOST CONTROLLER


4
20100190351
METHODS FOR REMOVING DIELECTRIC MATERIALS


5
20100190344
Methods of Forming Semiconductor Constructions


6
20100190314
Methods Of Forming Semiconductor Structures


7
20100190114
TOPOGRAPHY BASED PATTERNING


8
20100188921
VOLTAGE PROTECTION CIRCUIT FOR THIN OXIDE TRANSISTORS, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME


9
20100188906
STROBE APPARATUS, [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patent applications published on 29 July 2010 and assigned to Micron<br />
<span id="more-9949"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100192041.PGNR.&#038;OS=DN/20100192041RS=DN/20100192041" target="_blank">20100192041</a></td>
<td valign="top">MEMORY DEVICES AND METHODS FOR MANAGING ERROR REGIONS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100191999.PGNR.&#038;OS=DN/20100191999RS=DN/20100191999" target="_blank">20100191999</a></td>
<td valign="top">MEMORY DEVICE POWER MANAGERS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100191874.PGNR.&#038;OS=DN/20100191874RS=DN/20100191874" target="_blank">20100191874</a></td>
<td valign="top">HOST CONTROLLER</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100190351.PGNR.&#038;OS=DN/20100190351RS=DN/20100190351" target="_blank">20100190351</a></td>
<td valign="top">METHODS FOR REMOVING DIELECTRIC MATERIALS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100190344.PGNR.&#038;OS=DN/20100190344RS=DN/20100190344" target="_blank">20100190344</a></td>
<td valign="top">Methods of Forming Semiconductor Constructions</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100190314.PGNR.&#038;OS=DN/20100190314RS=DN/20100190314" target="_blank">20100190314</a></td>
<td valign="top">Methods Of Forming Semiconductor Structures</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100190114.PGNR.&#038;OS=DN/20100190114RS=DN/20100190114" target="_blank">20100190114</a></td>
<td valign="top">TOPOGRAPHY BASED PATTERNING</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188921.PGNR.&#038;OS=DN/20100188921RS=DN/20100188921" target="_blank">20100188921</a></td>
<td valign="top">VOLTAGE PROTECTION CIRCUIT FOR THIN OXIDE TRANSISTORS, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188906.PGNR.&#038;OS=DN/20100188906RS=DN/20100188906" target="_blank">20100188906</a></td>
<td valign="top">STROBE APPARATUS, SYSTEMS, AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188904.PGNR.&#038;OS=DN/20100188904RS=DN/20100188904" target="_blank">20100188904</a></td>
<td valign="top">MEMORY VOLTAGE CYCLE ADJUSTMENT</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188898.PGNR.&#038;OS=DN/20100188898RS=DN/20100188898" target="_blank">20100188898</a></td>
<td valign="top">REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188889.PGNR.&#038;OS=DN/20100188889RS=DN/20100188889" target="_blank">20100188889</a></td>
<td valign="top">BACK GATED SRAM CELL</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100188125.PGNR.&#038;OS=DN/20100188125RS=DN/20100188125" target="_blank">20100188125</a></td>
<td valign="top">DIGITAL LOCKED LOOPS AND METHODS WITH CONFIGURABLE OPERATING PARAMETERS</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100187668.PGNR.&#038;OS=DN/20100187668RS=DN/20100187668" target="_blank">20100187668</a></td>
<td valign="top">NOVEL BUILD-UP PACKAGE FOR INTEGRATED CIRCUIT DEVICES, AND METHODS OF MAKING SAME</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100186668.PGNR.&#038;OS=DN/20100186668RS=DN/20100186668" target="_blank">20100186668</a></td>
<td valign="top">ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING METAL BETA-DIKETIMINATE COMPOUNDS</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 27 July 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-27-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-27-july-2010/#comments</comments>
		<pubDate>Tue, 27 Jul 2010 14:07:43 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/micron-patents-granted-on-27-july-2010/</guid>
		<description><![CDATA[11 US patents granted on 27 July 2010 and assigned to Micron



1
7,765,426
Emerging bad block detection


2
7,765,424
System and method for injecting phase jitter into integrated circuit test signals


3
7,764,567
Word line driver circuitry and methods for using the same


4
7,764,563
Adjustable voltage regulator for providing a regulated output voltage


5
7,764,558
Hybrid sense amplifier and method, and memory device using same


6
7,764,554
I/O circuit with phase [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patents granted on 27 July 2010 and assigned to Micron<br />
<span id="more-9910"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,426" target="_blank" rel="nofollow">7,765,426</a></td>
<td valign="top">Emerging bad block detection</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,765,424" target="_blank" rel="nofollow">7,765,424</a></td>
<td valign="top">System and method for injecting phase jitter into integrated circuit test signals</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,567" target="_blank" rel="nofollow">7,764,567</a></td>
<td valign="top">Word line driver circuitry and methods for using the same</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,563" target="_blank" rel="nofollow">7,764,563</a></td>
<td valign="top">Adjustable voltage regulator for providing a regulated output voltage</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,558" target="_blank" rel="nofollow">7,764,558</a></td>
<td valign="top">Hybrid sense amplifier and method, and memory device using same</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,764,554" target="_blank" rel="nofollow">7,764,554</a></td>
<td valign="top">I/O circuit with phase mixer for slew rate control</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,933" target="_blank" rel="nofollow">7,763,933</a></td>
<td valign="top">Transistor constructions and processing methods</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,548" target="_blank" rel="nofollow">7,763,548</a></td>
<td valign="top">Microfeature workpiece processing system for, e.g., semiconductor wafer analysis</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,499" target="_blank" rel="nofollow">7,763,499</a></td>
<td valign="top">CMOS front end process compatible low stress light shield</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,497" target="_blank" rel="nofollow">7,763,497</a></td>
<td valign="top">Structure and method for forming a capacitively coupled chip-to-chip signaling interface</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,763,327" target="_blank" rel="nofollow">7,763,327</a></td>
<td valign="top">Methods using ozone for CVD deposited films</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patent applications published on 22 July 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-22-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-22-july-2010/#comments</comments>
		<pubDate>Thu, 22 Jul 2010 14:58:01 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9870</guid>
		<description><![CDATA[10 US patent applications published on 22 July 2010 and assigned to Micron



1
20100185830
LOGICAL ADDRESS OFFSET


2
20100185802
SOLID STATE MEMORY FORMATTING


3
20100185647
DEVICES, SYSTEMS, AND METHODS FOR COMMUNICATING PATTERN MATCHING RESULTS OF A PARALLEL PATTERN SEARCH ENGINE


4
20100182843
CURRENT SENSING FOR FLASH


5
20100182832
NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING


6
20100182822
DEVICE AND METHOD FOR USING DYNAMIC CELL PLATE SENSING IN A DRAM MEMORY CELL


7
20100182580
PHOTOLITHOGRAPHY SYSTEMS WITH LOCAL [...]]]></description>
			<content:encoded><![CDATA[<p>10 US patent applications published on 22 July 2010 and assigned to Micron<br />
<span id="more-9870"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100185830.PGNR.&#038;OS=DN/20100185830RS=DN/20100185830" target="_blank">20100185830</a></td>
<td valign="top">LOGICAL ADDRESS OFFSET</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100185802.PGNR.&#038;OS=DN/20100185802RS=DN/20100185802" target="_blank">20100185802</a></td>
<td valign="top">SOLID STATE MEMORY FORMATTING</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100185647.PGNR.&#038;OS=DN/20100185647RS=DN/20100185647" target="_blank">20100185647</a></td>
<td valign="top">DEVICES, SYSTEMS, AND METHODS FOR COMMUNICATING PATTERN MATCHING RESULTS OF A PARALLEL PATTERN SEARCH ENGINE</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182843.PGNR.&#038;OS=DN/20100182843RS=DN/20100182843" target="_blank">20100182843</a></td>
<td valign="top">CURRENT SENSING FOR FLASH</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182832.PGNR.&#038;OS=DN/20100182832RS=DN/20100182832" target="_blank">20100182832</a></td>
<td valign="top">NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182822.PGNR.&#038;OS=DN/20100182822RS=DN/20100182822" target="_blank">20100182822</a></td>
<td valign="top">DEVICE AND METHOD FOR USING DYNAMIC CELL PLATE SENSING IN A DRAM MEMORY CELL</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182580.PGNR.&#038;OS=DN/20100182580RS=DN/20100182580" target="_blank">20100182580</a></td>
<td valign="top">PHOTOLITHOGRAPHY SYSTEMS WITH LOCAL EXPOSURE CORRECTION AND ASSOCIATED METHODS</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182058.PGNR.&#038;OS=DN/20100182058RS=DN/20100182058" target="_blank">20100182058</a></td>
<td valign="top">DELAY LINES, METHODS FOR DELAYING A SIGNAL, AND DELAY LOCK LOOPS</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182057.PGNR.&#038;OS=DN/20100182057RS=DN/20100182057" target="_blank">20100182057</a></td>
<td valign="top">LOCKED LOOPS, BIAS GENERATORS, CHARGE PUMPS AND METHODS FOR GENERATING CONTROL VOLTAGES</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100182014.PGNR.&#038;OS=DN/20100182014RS=DN/20100182014" target="_blank">20100182014</a></td>
<td valign="top">SYSTEMS AND METHODS FOR DETECTING TERMINAL STATE AND SETTING OUTPUT DRIVER IMPEDANCE</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 20 July 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-20-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-20-july-2010/#comments</comments>
		<pubDate>Tue, 20 Jul 2010 14:56:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9829</guid>
		<description><![CDATA[24 US patents granted on 20 July 2010 and assigned to Micron



1
7,760,582
Apparatus for memory device wordline


2
7,760,533
Systems, methods and devices for arbitrating die stack position in a multi-bit stack device


3
7,760,532
Multi-bank memory


4
7,760,329
Optimized optical lithography illumination source for use during the manufacture of a semiconductor device


5
7,760,019
Adaptive operational transconductance amplifier load compensation


6
7,759,800
Microelectronics devices, having vias, and packaged microelectronic devices [...]]]></description>
			<content:encoded><![CDATA[<p>24 US patents granted on 20 July 2010 and assigned to Micron<br />
<span id="more-9829"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,582" target="_blank" rel="nofollow">7,760,582</a></td>
<td valign="top">Apparatus for memory device wordline</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,533" target="_blank" rel="nofollow">7,760,533</a></td>
<td valign="top">Systems, methods and devices for arbitrating die stack position in a multi-bit stack device</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,532" target="_blank" rel="nofollow">7,760,532</a></td>
<td valign="top">Multi-bank memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,329" target="_blank" rel="nofollow">7,760,329</a></td>
<td valign="top">Optimized optical lithography illumination source for use during the manufacture of a semiconductor device</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,760,019" target="_blank" rel="nofollow">7,760,019</a></td>
<td valign="top">Adaptive operational transconductance amplifier load compensation</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,800" target="_blank" rel="nofollow">7,759,800</a></td>
<td valign="top">Microelectronics devices, having vias, and packaged microelectronic devices having vias</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,785" target="_blank" rel="nofollow">7,759,785</a></td>
<td valign="top">Apparatus for packaging semiconductor devices, packaged semiconductor components, methods of manufacturing apparatus for packaging semiconductor devices, and methods of manufacturing semiconductor components</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,747" target="_blank" rel="nofollow">7,759,747</a></td>
<td valign="top">Tantalum aluminum oxynitride high-.kappa. dielectric</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,724" target="_blank" rel="nofollow">7,759,724</a></td>
<td valign="top">Memory cells having gate structure with multiple gates and multiple materials between the gates</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,717" target="_blank" rel="nofollow">7,759,717</a></td>
<td valign="top">Capacitors comprising dielectric regions having first and second oxide material portions of the same chemical compositon but different densities</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,715" target="_blank" rel="nofollow">7,759,715</a></td>
<td valign="top">Memory cell comprising dynamic random access memory (DRAM) nanoparticles and nonvolatile memory (NVM) nanoparticle</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,665" target="_blank" rel="nofollow">7,759,665</a></td>
<td valign="top">PCRAM device with switching glass layer</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,660" target="_blank" rel="nofollow">7,759,660</a></td>
<td valign="top">Electron beam lithography system</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,240" target="_blank" rel="nofollow">7,759,240</a></td>
<td valign="top">Use of palladium in IC manufacturing with conductive polymer bump</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,237" target="_blank" rel="nofollow">7,759,237</a></td>
<td valign="top">Method of forming lutetium and lanthanum dielectric structures</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,233" target="_blank" rel="nofollow">7,759,233</a></td>
<td valign="top">Methods for stressing semiconductor material structures to improve electron and/or hole mobility of transistor channels fabricated therefrom, and semiconductor devices including such structures</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,221" target="_blank" rel="nofollow">7,759,221</a></td>
<td valign="top">Methods for packaging microelectronic devices and microelectronic devices formed using such methods</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,197" target="_blank" rel="nofollow">7,759,197</a></td>
<td valign="top">Method of forming isolated features using pitch multiplication</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,193" target="_blank" rel="nofollow">7,759,193</a></td>
<td valign="top">Methods of forming a plurality of capacitors</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,187" target="_blank" rel="nofollow">7,759,187</a></td>
<td valign="top">Metal plating using seed film</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,183" target="_blank" rel="nofollow">7,759,183</a></td>
<td valign="top">Dual work function metal gates and methods of forming</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,154" target="_blank" rel="nofollow">7,759,154</a></td>
<td valign="top">Ultrashallow photodiode using indium</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,759,053" target="_blank" rel="nofollow">7,759,053</a></td>
<td valign="top">Methods of fabricating integrated circuitry</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,385" target="_blank" rel="nofollow">7,757,385</a></td>
<td valign="top">System for fabricating semiconductor components with through wire interconnects</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patent applications published on 15 July 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-15-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-15-july-2010/#comments</comments>
		<pubDate>Thu, 15 Jul 2010 15:47:38 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9789</guid>
		<description><![CDATA[12 US patent applications published on 15 July 2010 and assigned to Micron



1
20100180150
SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM


2
20100180105
MODIFYING COMMANDS


3
20100178748
Methods of Etching Trenches Into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes


4
20100177578
TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING


5
20100177574
SYSTEM [...]]]></description>
			<content:encoded><![CDATA[<p>12 US patent applications published on 15 July 2010 and assigned to Micron<br />
<span id="more-9789"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100180150.PGNR.&#038;OS=DN/20100180150RS=DN/20100180150" target="_blank">20100180150</a></td>
<td valign="top">SYSTEMS AND METHODS FOR MONITORING A MEMORY SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100180105.PGNR.&#038;OS=DN/20100180105RS=DN/20100180105" target="_blank">20100180105</a></td>
<td valign="top">MODIFYING COMMANDS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100178748.PGNR.&#038;OS=DN/20100178748RS=DN/20100178748" target="_blank">20100178748</a></td>
<td valign="top">Methods of Etching Trenches Into Silicon of a Semiconductor Substrate, Methods of Forming Trench Isolation in Silicon of a Semiconductor Substrate, and Methods of Forming a Plurality of Diodes</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177578.PGNR.&#038;OS=DN/20100177578RS=DN/20100177578" target="_blank">20100177578</a></td>
<td valign="top">TRI-STATE DRIVER CIRCUITS HAVING AUTOMATIC HIGH-IMPEDANCE ENABLING</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177574.PGNR.&#038;OS=DN/20100177574RS=DN/20100177574" target="_blank">20100177574</a></td>
<td valign="top">SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177571.PGNR.&#038;OS=DN/20100177571RS=DN/20100177571" target="_blank">20100177571</a></td>
<td valign="top">MEMORY BANK SIGNAL COUPLING BUFFER AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177564.PGNR.&#038;OS=DN/20100177564RS=DN/20100177564" target="_blank">20100177564</a></td>
<td valign="top">METHOD FOR DETECTING FLASH PROGRAM FAILURES</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177561.PGNR.&#038;OS=DN/20100177561RS=DN/20100177561" target="_blank">20100177561</a></td>
<td valign="top">MEMORY CELL HAVING NONMAGNETIC FILAMENT CONTACT AND METHODS OF OPERATING AND FABRICATING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177557.PGNR.&#038;OS=DN/20100177557RS=DN/20100177557" target="_blank">20100177557</a></td>
<td valign="top">STT-MRAM CELL STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100177490.PGNR.&#038;OS=DN/20100177490RS=DN/20100177490" target="_blank">20100177490</a></td>
<td valign="top">COMPUTER MODULES WITH SMALL THICKNESSES AND ASSOCIATED METHODS OF MANUFACTURING</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100176367.PGNR.&#038;OS=DN/20100176367RS=DN/20100176367" target="_blank">20100176367</a></td>
<td valign="top">MEMORY CELL HAVING DIELECTRIC MEMORY ELEMENT</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100176083.PGNR.&#038;OS=DN/20100176083RS=DN/20100176083" target="_blank">20100176083</a></td>
<td valign="top">METHOD AND APPARATUS FOR REMOVING ADJACENT CONDUCTIVE AND NON-CONDUCTIVE MATERIALS OF A MICROELECTRONIC SUBSTRATE</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 13 July 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-13-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-13-july-2010/#comments</comments>
		<pubDate>Tue, 13 Jul 2010 16:14:17 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9749</guid>
		<description><![CDATA[18 US patents granted on 13 July 2010 and assigned to Micron



1
RE41,441
Output buffer having inherently precise data masking


2
7,757,061
System and method for decoding commands based on command signals and operating state


3
7,755,940
Method, apparatus, and system for erasing memory


4
7,755,939
System and devices including memory resistant to program disturb and methods of using, making, and operating the same


5
7,755,684
Row driver circuitry [...]]]></description>
			<content:encoded><![CDATA[<p>18 US patents granted on 13 July 2010 and assigned to Micron<br />
<span id="more-9749"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=RE41,441" target="_blank" rel="nofollow">RE41,441</a></td>
<td valign="top">Output buffer having inherently precise data masking</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,757,061" target="_blank" rel="nofollow">7,757,061</a></td>
<td valign="top">System and method for decoding commands based on command signals and operating state</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,940" target="_blank" rel="nofollow">7,755,940</a></td>
<td valign="top">Method, apparatus, and system for erasing memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,939" target="_blank" rel="nofollow">7,755,939</a></td>
<td valign="top">System and devices including memory resistant to program disturb and methods of using, making, and operating the same</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,684" target="_blank" rel="nofollow">7,755,684</a></td>
<td valign="top">Row driver circuitry for imaging devices and related method of operation</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,570" target="_blank" rel="nofollow">7,755,570</a></td>
<td valign="top">Microdisplay and interface on a single chip</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,404" target="_blank" rel="nofollow">7,755,404</a></td>
<td valign="top">Delay locked loop circuit and method</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,385" target="_blank" rel="nofollow">7,755,385</a></td>
<td valign="top">Method for operating an electronic device with reduced pin capacitance</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,204" target="_blank" rel="nofollow">7,755,204</a></td>
<td valign="top">Stacked die module including multiple adhesives that cure at different temperatures</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,755,119" target="_blank" rel="nofollow">7,755,119</a></td>
<td valign="top">Method and apparatus for reducing imager floating diffusion leakage</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,618" target="_blank" rel="nofollow">7,754,618</a></td>
<td valign="top">Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,612" target="_blank" rel="nofollow">7,754,612</a></td>
<td valign="top">Methods and apparatuses for removing polysilicon from semiconductor workpieces</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,576" target="_blank" rel="nofollow">7,754,576</a></td>
<td valign="top">Method of forming inside rough and outside smooth HSG electrodes and capacitor structure</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,532" target="_blank" rel="nofollow">7,754,532</a></td>
<td valign="top">High density chip packages, methods of forming, and systems including same</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,531" target="_blank" rel="nofollow">7,754,531</a></td>
<td valign="top">Method for packaging microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,522" target="_blank" rel="nofollow">7,754,522</a></td>
<td valign="top">Phase change memory structures and methods</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,399" target="_blank" rel="nofollow">7,754,399</a></td>
<td valign="top">Methods of forming reticles</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,754,395" target="_blank" rel="nofollow">7,754,395</a></td>
<td valign="top">Methods of forming and using reticles</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patent applications published on 08 July 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-08-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-08-july-2010/#comments</comments>
		<pubDate>Thu, 08 Jul 2010 13:53:39 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9709</guid>
		<description><![CDATA[18 US patent applications published on 08 July 2010 and assigned to Micron



1
20100175130
Pattern-Recognition Processor with Matching-Data Reporting Module


2
20100174929
Method and Systems for Power Consumption Management of a Pattern-Recognition Processor


3
20100174887
Buses for Pattern-Recognition Processors


4
20100174855
MEMORY DEVICE CONTROLLER


5
20100174851
MEMORY SYSTEM CONTROLLER


6
20100173571
CENTERLESS GRINDING METHOD


7
20100173498
TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS


8
20100173460
VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME


9
20100173456
Methods [...]]]></description>
			<content:encoded><![CDATA[<p>18 US patent applications published on 08 July 2010 and assigned to Micron<br />
<span id="more-9709"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100175130.PGNR.&#038;OS=DN/20100175130RS=DN/20100175130" target="_blank">20100175130</a></td>
<td valign="top">Pattern-Recognition Processor with Matching-Data Reporting Module</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100174929.PGNR.&#038;OS=DN/20100174929RS=DN/20100174929" target="_blank">20100174929</a></td>
<td valign="top">Method and Systems for Power Consumption Management of a Pattern-Recognition Processor</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100174887.PGNR.&#038;OS=DN/20100174887RS=DN/20100174887" target="_blank">20100174887</a></td>
<td valign="top">Buses for Pattern-Recognition Processors</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100174855.PGNR.&#038;OS=DN/20100174855RS=DN/20100174855" target="_blank">20100174855</a></td>
<td valign="top">MEMORY DEVICE CONTROLLER</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100174851.PGNR.&#038;OS=DN/20100174851RS=DN/20100174851" target="_blank">20100174851</a></td>
<td valign="top">MEMORY SYSTEM CONTROLLER</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100173571.PGNR.&#038;OS=DN/20100173571RS=DN/20100173571" target="_blank">20100173571</a></td>
<td valign="top">CENTERLESS GRINDING METHOD</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100173498.PGNR.&#038;OS=DN/20100173498RS=DN/20100173498" target="_blank">20100173498</a></td>
<td valign="top">TRIM PROCESS FOR CRITICAL DIMENSION CONTROL FOR INTEGRATED CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100173460.PGNR.&#038;OS=DN/20100173460RS=DN/20100173460" target="_blank">20100173460</a></td>
<td valign="top">VERTICAL TRANSISTOR, MEMORY CELL, DEVICE, SYSTEM AND METHOD OF FORMING SAME</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100173456.PGNR.&#038;OS=DN/20100173456RS=DN/20100173456" target="_blank">20100173456</a></td>
<td valign="top">Methods of Forming Field Effect Transistors, Methods of Forming Field Effect Transistor Gates, Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array and Circuitry Peripheral to the Gate Array, and Methods of Forming Integrated Circuitry Comprising a Transistor Gate Array Including First Gates and Second Grounded Isolation Gates</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100173454.PGNR.&#038;OS=DN/20100173454RS=DN/20100173454" target="_blank">20100173454</a></td>
<td valign="top">MICROELECTRONIC PACKAGES WITH LEADFRAMES, INCLUDING LEADFRAMES CONFIGURED FOR STACKED DIE PACKAGES, AND ASSOCIATED SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100172186.PGNR.&#038;OS=DN/20100172186RS=DN/20100172186" target="_blank">20100172186</a></td>
<td valign="top">PROGRAMMING AND/OR ERASING A MEMORY DEVICE IN RESPONSE TO ITS PROGRAM AND/OR ERASE HISTORY</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100172175.PGNR.&#038;OS=DN/20100172175RS=DN/20100172175" target="_blank">20100172175</a></td>
<td valign="top">MEMORY DEVICE AND METHOD HAVING CHARGE LEVEL ASSIGNMENTS SELECTED TO MINIMIZE SIGNAL COUPLING</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100172059.PGNR.&#038;OS=DN/20100172059RS=DN/20100172059" target="_blank">20100172059</a></td>
<td valign="top">OVER-LIMIT ELECTRICAL CONDITION PROTECTION CIRCUITS FOR INTEGRATED CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171217.PGNR.&#038;OS=DN/20100171217RS=DN/20100171217" target="_blank">20100171217</a></td>
<td valign="top">THROUGH-WAFER INTERCONNECTS FOR PHOTOIMAGER AND MEMORY WAFERS</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171178.PGNR.&#038;OS=DN/20100171178RS=DN/20100171178" target="_blank">20100171178</a></td>
<td valign="top">SEMICONDUCTOR DEVICES INCLUDING DUAL GATE STRUCTURES AND METHODS OF FORMING SUCH SEMICONDUCTOR DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171176.PGNR.&#038;OS=DN/20100171176RS=DN/20100171176" target="_blank">20100171176</a></td>
<td valign="top">Integrated Circuitry And Methods Of Forming A Semiconductor-On-Insulator Substrate</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171170.PGNR.&#038;OS=DN/20100171170RS=DN/20100171170" target="_blank">20100171170</a></td>
<td valign="top">SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100171089.PGNR.&#038;OS=DN/20100171089RS=DN/20100171089" target="_blank">20100171089</a></td>
<td valign="top">DIELECTRIC LAYERS AND MEMORY CELLS INCLUDING METAL-DOPED ALUMINA</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 06 July 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-06-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-06-july-2010/#comments</comments>
		<pubDate>Tue, 06 Jul 2010 14:34:49 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9670</guid>
		<description><![CDATA[29 US patents granted on 06 July 2010 and assigned to Micron



1
7,752,381
Version based non-volatile memory translation layer


2
7,751,634
Compression system for integrated sensor devices


3
7,751,263
Data retention kill function


4
7,751,260
Memory device having strobe terminals with multiple functions


5
7,751,253
Analog sensing of memory cells with a source follower driver in a semiconductor memory device


6
7,751,246
Charge loss compensation during programming of a memory device


7
7,751,245
Programming sequence [...]]]></description>
			<content:encoded><![CDATA[<p>29 US patents granted on 06 July 2010 and assigned to Micron<br />
<span id="more-9670"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,752,381" target="_blank" rel="nofollow">7,752,381</a></td>
<td valign="top">Version based non-volatile memory translation layer</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,634" target="_blank" rel="nofollow">7,751,634</a></td>
<td valign="top">Compression system for integrated sensor devices</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,263" target="_blank" rel="nofollow">7,751,263</a></td>
<td valign="top">Data retention kill function</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,260" target="_blank" rel="nofollow">7,751,260</a></td>
<td valign="top">Memory device having strobe terminals with multiple functions</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,253" target="_blank" rel="nofollow">7,751,253</a></td>
<td valign="top">Analog sensing of memory cells with a source follower driver in a semiconductor memory device</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,246" target="_blank" rel="nofollow">7,751,246</a></td>
<td valign="top">Charge loss compensation during programming of a memory device</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,245" target="_blank" rel="nofollow">7,751,245</a></td>
<td valign="top">Programming sequence in NAND memory</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,242" target="_blank" rel="nofollow">7,751,242</a></td>
<td valign="top">NAND memory device and programming methods</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,236" target="_blank" rel="nofollow">7,751,236</a></td>
<td valign="top">MEM suspended gate non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,751,228" target="_blank" rel="nofollow">7,751,228</a></td>
<td valign="top">Dielectric relaxation memory</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,449" target="_blank" rel="nofollow">7,750,449</a></td>
<td valign="top">Packaged semiconductor components having substantially rigid support members and methods of packaging semiconductor components</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,395" target="_blank" rel="nofollow">7,750,395</a></td>
<td valign="top">Scalable Flash/NV structures and devices with extended endurance</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,389" target="_blank" rel="nofollow">7,750,389</a></td>
<td valign="top">NROM memory cell, memory array, related devices and methods</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,379" target="_blank" rel="nofollow">7,750,379</a></td>
<td valign="top">Metal-substituted transistor gates</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,750,344" target="_blank" rel="nofollow">7,750,344</a></td>
<td valign="top">Doped aluminum oxide dielectrics</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,899" target="_blank" rel="nofollow">7,749,899</a></td>
<td valign="top">Microelectronic workpieces and methods and systems for forming interconnects in microelectronic workpieces</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,887" target="_blank" rel="nofollow">7,749,887</a></td>
<td valign="top">Methods of fluxless micro-piercing of solder balls, and resulting devices</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,885" target="_blank" rel="nofollow">7,749,885</a></td>
<td valign="top">Semiconductor processing methods, methods of forming contact pads, and methods of forming electrical connections between metal-containing layers</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,882" target="_blank" rel="nofollow">7,749,882</a></td>
<td valign="top">Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,879" target="_blank" rel="nofollow">7,749,879</a></td>
<td valign="top">ALD of silicon films on germanium</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,860" target="_blank" rel="nofollow">7,749,860</a></td>
<td valign="top">Method for forming a self-aligned T-shaped isolation trench</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,849" target="_blank" rel="nofollow">7,749,849</a></td>
<td valign="top">Methods of selectively oxidizing semiconductor structures, and structures resulting therefrom</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,848" target="_blank" rel="nofollow">7,749,848</a></td>
<td valign="top">Band-engineered multi-gated non-volatile memory device with enhanced attributes</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,837" target="_blank" rel="nofollow">7,749,837</a></td>
<td valign="top">High coupling memory cell</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,808" target="_blank" rel="nofollow">7,749,808</a></td>
<td valign="top">Stacked microelectronic devices and methods for manufacturing microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">26</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,786" target="_blank" rel="nofollow">7,749,786</a></td>
<td valign="top">Methods of forming imager systems</td>
</tr>
<tr>
<td valign="top" align="right">27</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,663" target="_blank" rel="nofollow">7,749,663</a></td>
<td valign="top">Method for adjusting dimensions of photomask features</td>
</tr>
<tr>
<td valign="top" align="right">28</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,349" target="_blank" rel="nofollow">7,749,349</a></td>
<td valign="top">Methods and systems for releasably attaching support members to microfeature workpieces</td>
</tr>
<tr>
<td valign="top" align="right">29</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,749,327" target="_blank" rel="nofollow">7,749,327</a></td>
<td valign="top">Methods for treating surfaces</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patent applications published on 01 July 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-01-july-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-01-july-2010/#comments</comments>
		<pubDate>Thu, 01 Jul 2010 13:50:28 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9630</guid>
		<description><![CDATA[10 US patent applications published on 01 July 2010 and assigned to Micron



1
20100169538
SYSTEMS, METHODS, AND DEVICES FOR CONFIGURING A DEVICE


2
20100167542
Methods of Titanium Deposition


3
20100167521
Semiconductor Processing Methods


4
20100167479
EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY


5
20100167451
METHODS OF MANUFACTURING IMAGING DEVICE PACKAGES


6
20100165747
NON-VOLATILE MEMORY CELL HEALING


7
20100165741
DYNAMIC PASS VOLTAGE


8
20100165739
NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING


9
20100165692
VARIABLE MEMORY REFRESH DEVICES AND METHODS


10
20100164588
GENERATING A FULL RAIL SIGNAL


]]></description>
			<content:encoded><![CDATA[<p>10 US patent applications published on 01 July 2010 and assigned to Micron<br />
<span id="more-9630"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100169538.PGNR.&#038;OS=DN/20100169538RS=DN/20100169538" target="_blank">20100169538</a></td>
<td valign="top">SYSTEMS, METHODS, AND DEVICES FOR CONFIGURING A DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100167542.PGNR.&#038;OS=DN/20100167542RS=DN/20100167542" target="_blank">20100167542</a></td>
<td valign="top">Methods of Titanium Deposition</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100167521.PGNR.&#038;OS=DN/20100167521RS=DN/20100167521" target="_blank">20100167521</a></td>
<td valign="top">Semiconductor Processing Methods</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100167479.PGNR.&#038;OS=DN/20100167479RS=DN/20100167479" target="_blank">20100167479</a></td>
<td valign="top">EMBEDDED TRAP DIRECT TUNNEL NON-VOLATILE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100167451.PGNR.&#038;OS=DN/20100167451RS=DN/20100167451" target="_blank">20100167451</a></td>
<td valign="top">METHODS OF MANUFACTURING IMAGING DEVICE PACKAGES</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100165747.PGNR.&#038;OS=DN/20100165747RS=DN/20100165747" target="_blank">20100165747</a></td>
<td valign="top">NON-VOLATILE MEMORY CELL HEALING</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100165741.PGNR.&#038;OS=DN/20100165741RS=DN/20100165741" target="_blank">20100165741</a></td>
<td valign="top">DYNAMIC PASS VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100165739.PGNR.&#038;OS=DN/20100165739RS=DN/20100165739" target="_blank">20100165739</a></td>
<td valign="top">NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100165692.PGNR.&#038;OS=DN/20100165692RS=DN/20100165692" target="_blank">20100165692</a></td>
<td valign="top">VARIABLE MEMORY REFRESH DEVICES AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100164588.PGNR.&#038;OS=DN/20100164588RS=DN/20100164588" target="_blank">20100164588</a></td>
<td valign="top">GENERATING A FULL RAIL SIGNAL</td>
</tr>
</table>
]]></content:encoded>
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		</item>
		<item>
		<title>Micron patents granted on 29 June 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-29-june-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-29-june-2010/#comments</comments>
		<pubDate>Tue, 29 Jun 2010 14:23:11 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=9588</guid>
		<description><![CDATA[23 US patents granted on 29 June 2010 and assigned to Micron



1
7,747,933
Method and apparatus for detecting communication errors on a bus


2
7,747,903
Error correction for memory


3
7,747,890
Method and apparatus of high-speed input sampling


4
7,747,090
Scan line to block re-ordering buffer for image compression


5
7,746,959
Method and system for generating reference voltages for signal receivers


6
7,746,720
Techniques for reducing leakage current in memory devices


7
7,746,710
Data bus [...]]]></description>
			<content:encoded><![CDATA[<p>23 US patents granted on 29 June 2010 and assigned to Micron<br />
<span id="more-9588"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,933" target="_blank" rel="nofollow">7,747,933</a></td>
<td valign="top">Method and apparatus for detecting communication errors on a bus</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,903" target="_blank" rel="nofollow">7,747,903</a></td>
<td valign="top">Error correction for memory</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,890" target="_blank" rel="nofollow">7,747,890</a></td>
<td valign="top">Method and apparatus of high-speed input sampling</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,747,090" target="_blank" rel="nofollow">7,747,090</a></td>
<td valign="top">Scan line to block re-ordering buffer for image compression</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,959" target="_blank" rel="nofollow">7,746,959</a></td>
<td valign="top">Method and system for generating reference voltages for signal receivers</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,720" target="_blank" rel="nofollow">7,746,720</a></td>
<td valign="top">Techniques for reducing leakage current in memory devices</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,710" target="_blank" rel="nofollow">7,746,710</a></td>
<td valign="top">Data bus power-reduced semiconductor storage apparatus</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,701" target="_blank" rel="nofollow">7,746,701</a></td>
<td valign="top">Semiconductor memory device having bit line pre-charge unit separated from data register</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,700" target="_blank" rel="nofollow">7,746,700</a></td>
<td valign="top">NAND architecture memory devices and operation</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,691" target="_blank" rel="nofollow">7,746,691</a></td>
<td valign="top">Methods and apparatus utilizing predicted coupling effect in the programming of non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,398" target="_blank" rel="nofollow">7,746,398</a></td>
<td valign="top">Wide dynamic range active pixel with knee response</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,746,170" target="_blank" rel="nofollow">7,746,170</a></td>
<td valign="top">Class AB amplifier and imagers and systems using same</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,944" target="_blank" rel="nofollow">7,745,944</a></td>
<td valign="top">Microelectronic devices having intermediate contacts for connection to interposer substrates, and associated methods of packaging microelectronic devices with intermediate contacts</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,942" target="_blank" rel="nofollow">7,745,942</a></td>
<td valign="top">Die package and probe card structures and fabrication methods</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,934" target="_blank" rel="nofollow">7,745,934</a></td>
<td valign="top">Integrated circuit and seed layers</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,920" target="_blank" rel="nofollow">7,745,920</a></td>
<td valign="top">Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,900" target="_blank" rel="nofollow">7,745,900</a></td>
<td valign="top">Method and apparatus providing refractive index structure for a device capturing or displaying images</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,873" target="_blank" rel="nofollow">7,745,873</a></td>
<td valign="top">Ultra-thin body vertical tunneling transistor</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,808" target="_blank" rel="nofollow">7,745,808</a></td>
<td valign="top">Differential negative resistance memory</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,319" target="_blank" rel="nofollow">7,745,319</a></td>
<td valign="top">System and method for fabricating a fin field effect transistor</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,295" target="_blank" rel="nofollow">7,745,295</a></td>
<td valign="top">Methods of forming memory cells</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,283" target="_blank" rel="nofollow">7,745,283</a></td>
<td valign="top">Method of fabricating memory transistor</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,745,231" target="_blank" rel="nofollow">7,745,231</a></td>
<td valign="top">Resistive memory cell fabrication methods and devices</td>
</tr>
</table>
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