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	<title>Latest Patents &#187; Micron</title>
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	<description>Latest Patents of Leading Technology Companies</description>
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		<title>Micron patent applications published on 02 February 2012</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-02-february-2012/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-02-february-2012/#comments</comments>
		<pubDate>Fri, 03 Feb 2012 03:32:13 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16400</guid>
		<description><![CDATA[8 US patent applications published on 02 February 2012 and assigned to Micron 1 20120030638 METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME 2 20120030545 ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING 3 20120030529 REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS 4 20120030452 MODIFYING COMMANDS [...]]]></description>
			<content:encoded><![CDATA[<p>8 US patent applications published on 02 February 2012 and assigned to Micron<br />
<span id="more-16400"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120030638.PGNR.&#038;OS=DN/20120030638RS=DN/20120030638" target="_blank">20120030638</a></td>
<td valign="top">METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120030545.PGNR.&#038;OS=DN/20120030545RS=DN/20120030545" target="_blank">20120030545</a></td>
<td valign="top">ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120030529.PGNR.&#038;OS=DN/20120030529RS=DN/20120030529" target="_blank">20120030529</a></td>
<td valign="top">REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120030452.PGNR.&#038;OS=DN/20120030452RS=DN/20120030452" target="_blank">20120030452</a></td>
<td valign="top">MODIFYING COMMANDS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120028410.PGNR.&#038;OS=DN/20120028410RS=DN/20120028410" target="_blank">20120028410</a></td>
<td valign="top">METHODS OF FORMING GERMANIUM-ANTIMONY-TELLURIUM MATERIALS AND A METHOD OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE INCLUDING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120026816.PGNR.&#038;OS=DN/20120026816RS=DN/20120026816" target="_blank">20120026816</a></td>
<td valign="top">DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120026792.PGNR.&#038;OS=DN/20120026792RS=DN/20120026792" target="_blank">20120026792</a></td>
<td valign="top">ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120025402.PGNR.&#038;OS=DN/20120025402RS=DN/20120025402" target="_blank">20120025402</a></td>
<td valign="top">METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICE STRUCTURES INCLUDING A UNIFORM PATTERN OF CONDUCTIVE LINES</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 31 January 2012</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-31-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-31-january-2012/#comments</comments>
		<pubDate>Tue, 31 Jan 2012 21:43:57 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16358</guid>
		<description><![CDATA[14 US patents granted on 31 January 2012 and assigned to Micron 1 8,107,344 Phase masks for use in holographic data storage 2 8,107,305 Integrated circuit memory operation apparatus and methods 3 8,107,296 Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device 4 8,107,218 Capacitors 5 8,106,644 Reference circuit [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patents granted on 31 January 2012 and assigned to Micron<br />
<span id="more-16358"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,107,344" target="_blank" rel="nofollow">8,107,344</a></td>
<td valign="top">Phase masks for use in holographic data storage</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,107,305" target="_blank" rel="nofollow">8,107,305</a></td>
<td valign="top">Integrated circuit memory operation apparatus and methods</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,107,296" target="_blank" rel="nofollow">8,107,296</a></td>
<td valign="top">Mitigation of data corruption from back pattern and program disturb in a non-volatile memory device</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,107,218" target="_blank" rel="nofollow">8,107,218</a></td>
<td valign="top">Capacitors</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,106,644" target="_blank" rel="nofollow">8,106,644</a></td>
<td valign="top">Reference circuit with start-up control, generator, device, system and method including same</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,106,520" target="_blank" rel="nofollow">8,106,520</a></td>
<td valign="top">Signal delivery in stacked device</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,106,491" target="_blank" rel="nofollow">8,106,491</a></td>
<td valign="top">Methods of forming stacked semiconductor devices with a leadframe and associated assemblies</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,106,488" target="_blank" rel="nofollow">8,106,488</a></td>
<td valign="top">Wafer level packaging</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,106,438" target="_blank" rel="nofollow">8,106,438</a></td>
<td valign="top">Stud capacitor device and fabrication method</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,105,956" target="_blank" rel="nofollow">8,105,956</a></td>
<td valign="top">Methods of forming silicon oxides and methods of forming interlevel dielectrics</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,105,896" target="_blank" rel="nofollow">8,105,896</a></td>
<td valign="top">Methods of forming capacitors</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,105,862" target="_blank" rel="nofollow">8,105,862</a></td>
<td valign="top">Imager with tuned color filter</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,105,858" target="_blank" rel="nofollow">8,105,858</a></td>
<td valign="top">CMOS imager having a nitride dielectric</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,105,131" target="_blank" rel="nofollow">8,105,131</a></td>
<td valign="top">Method and apparatus for removing material from microfeature workpieces</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 26 January 2012</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-26-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-26-january-2012/#comments</comments>
		<pubDate>Fri, 27 Jan 2012 00:02:19 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16318</guid>
		<description><![CDATA[11 US patent applications published on 26 January 2012 and assigned to Micron 1 20120023294 MEMORY DEVICE AND METHOD HAVING ON-BOARD PROCESSING LOGIC FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME 2 20120021610 Methods of Forming Material on a Substrate, and a Method of Forming a Field Effect Transistor Gate Oxide on [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patent applications published on 26 January 2012 and assigned to Micron<br />
<span id="more-16318"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120023294.PGNR.&#038;OS=DN/20120023294RS=DN/20120023294" target="_blank">20120023294</a></td>
<td valign="top">MEMORY DEVICE AND METHOD HAVING ON-BOARD PROCESSING LOGIC FOR FACILITATING INTERFACE WITH MULTIPLE PROCESSORS, AND COMPUTER SYSTEM USING SAME</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120021610.PGNR.&#038;OS=DN/20120021610RS=DN/20120021610" target="_blank">20120021610</a></td>
<td valign="top">Methods of Forming Material on a Substrate, and a Method of Forming a Field Effect Transistor Gate Oxide on a Substrate</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120021601.PGNR.&#038;OS=DN/20120021601RS=DN/20120021601" target="_blank">20120021601</a></td>
<td valign="top">Methods of Forming Through Substrate Interconnects</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120021594.PGNR.&#038;OS=DN/20120021594RS=DN/20120021594" target="_blank">20120021594</a></td>
<td valign="top">Methods of Forming a Plurality of Transistor Gates, and Methods of Forming a Plurality of Transistor Gates Having at Least Two Different Work Functions</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120021587.PGNR.&#038;OS=DN/20120021587RS=DN/20120021587" target="_blank">20120021587</a></td>
<td valign="top">Systems and Methods for Forming Metal Oxide Layers</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120021573.PGNR.&#038;OS=DN/20120021573RS=DN/20120021573" target="_blank">20120021573</a></td>
<td valign="top">Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120019349.PGNR.&#038;OS=DN/20120019349RS=DN/20120019349" target="_blank">20120019349</a></td>
<td valign="top">CONFINED RESISTANCE VARIABLE MEMORY CELLS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120019293.PGNR.&#038;OS=DN/20120019293RS=DN/20120019293" target="_blank">20120019293</a></td>
<td valign="top">DELAY LOCK LOOP PHASE GLITCH ERROR FILTER</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120018887.PGNR.&#038;OS=DN/20120018887RS=DN/20120018887" target="_blank">20120018887</a></td>
<td valign="top">MICROELECTRONIC DEVICE PACKAGES, STACKED MICROELECTRONIC DEVICE PACKAGES, AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120018789.PGNR.&#038;OS=DN/20120018789RS=DN/20120018789" target="_blank">20120018789</a></td>
<td valign="top">Systems and Devices Including Multi-Gate Transistors and Methods of Using, Making, and Operating the Same</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120018693.PGNR.&#038;OS=DN/20120018693RS=DN/20120018693" target="_blank">20120018693</a></td>
<td valign="top">CONFINED RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 24 January 2012</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-24-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-24-january-2012/#comments</comments>
		<pubDate>Tue, 24 Jan 2012 15:32:59 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16278</guid>
		<description><![CDATA[25 US patents granted on 24 January 2012 and assigned to Micron 1 8,103,940 Programming error correction code into a solid state memory device with varying bits per cell 2 8,103,936 System and method for data read of a synchronous serial interface NAND 3 8,103,928 Multiple device apparatus, systems, and methods 4 8,103,898 Explicit skew [...]]]></description>
			<content:encoded><![CDATA[<p>25 US patents granted on 24 January 2012 and assigned to Micron<br />
<span id="more-16278"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,103,940" target="_blank" rel="nofollow">8,103,940</a></td>
<td valign="top">Programming error correction code into a solid state memory device with varying bits per cell</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,103,936" target="_blank" rel="nofollow">8,103,936</a></td>
<td valign="top">System and method for data read of a synchronous serial interface NAND</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,103,928" target="_blank" rel="nofollow">8,103,928</a></td>
<td valign="top">Multiple device apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,103,898" target="_blank" rel="nofollow">8,103,898</a></td>
<td valign="top">Explicit skew interface for mitigating crosstalk and simultaneous switching noise</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,103,805" target="_blank" rel="nofollow">8,103,805</a></td>
<td valign="top">Configuration finalization on first valid NAND command</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,906" target="_blank" rel="nofollow">8,102,906</a></td>
<td valign="top">Fractional-rate decision feedback equalization useful in a data transmission system</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,723" target="_blank" rel="nofollow">8,102,723</a></td>
<td valign="top">Memory device bit line sensing system and method that compensates for bit line resistance variations</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,715" target="_blank" rel="nofollow">8,102,715</a></td>
<td valign="top">Power-off apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,710" target="_blank" rel="nofollow">8,102,710</a></td>
<td valign="top">System and method for setting access and modification for synchronous serial interface NAND</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,709" target="_blank" rel="nofollow">8,102,709</a></td>
<td valign="top">Transistor having peripheral channel</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,707" target="_blank" rel="nofollow">8,102,707</a></td>
<td valign="top">Non-volatile multilevel memory cells</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,706" target="_blank" rel="nofollow">8,102,706</a></td>
<td valign="top">Programming a memory with varying bits per cell</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,700" target="_blank" rel="nofollow">8,102,700</a></td>
<td valign="top">Unidirectional spin torque transfer magnetic memory cell structure</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,295" target="_blank" rel="nofollow">8,102,295</a></td>
<td valign="top">Integrators for delta-sigma modulators</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,013" target="_blank" rel="nofollow">8,102,013</a></td>
<td valign="top">Lanthanide doped TiO.sub.x films</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,008" target="_blank" rel="nofollow">8,102,008</a></td>
<td valign="top">Integrated circuit with buried digit line</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,102,006" target="_blank" rel="nofollow">8,102,006</a></td>
<td valign="top">Different gate oxides thicknesses for different transistors in an integrated circuit</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,992" target="_blank" rel="nofollow">8,101,992</a></td>
<td valign="top">Memory array with surrounding gate access transistors and capacitors with global and staggered local bit lines</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,936" target="_blank" rel="nofollow">8,101,936</a></td>
<td valign="top">SnSe-based limited reprogrammable cell</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,903" target="_blank" rel="nofollow">8,101,903</a></td>
<td valign="top">Method, apparatus and system providing holographic layer as micro-lens and color filter array in an imager</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,497" target="_blank" rel="nofollow">8,101,497</a></td>
<td valign="top">Self-aligned trench formation</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,464" target="_blank" rel="nofollow">8,101,464</a></td>
<td valign="top">Microelectronic devices and methods for manufacturing microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,459" target="_blank" rel="nofollow">8,101,459</a></td>
<td valign="top">Methods for assembling semiconductor devices in stacked arrangements by positioning spacers therebetween</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,454" target="_blank" rel="nofollow">8,101,454</a></td>
<td valign="top">Method of forming pixel cell having a grated interface</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,101,261" target="_blank" rel="nofollow">8,101,261</a></td>
<td valign="top">One-dimensional arrays of block copolymer cylinders and applications thereof</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 19 January 2012</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-19-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-19-january-2012/#comments</comments>
		<pubDate>Thu, 19 Jan 2012 16:46:51 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16237</guid>
		<description><![CDATA[13 US patent applications published on 19 January 2012 and assigned to Micron 1 20120016651 Simulating the Transmission of Asymmetric Signals in a Computer System 2 20120016650 Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System 3 20120015526 Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition [...]]]></description>
			<content:encoded><![CDATA[<p>13 US patent applications published on 19 January 2012 and assigned to Micron<br />
<span id="more-16237"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120016651.PGNR.&#038;OS=DN/20120016651RS=DN/20120016651" target="_blank">20120016651</a></td>
<td valign="top">Simulating the Transmission of Asymmetric Signals in a Computer System</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120016650.PGNR.&#038;OS=DN/20120016650RS=DN/20120016650" target="_blank">20120016650</a></td>
<td valign="top">Simulating the Transmission and Simultaneous Switching Output Noise of Signals in a Computer System</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120015526.PGNR.&#038;OS=DN/20120015526RS=DN/20120015526" target="_blank">20120015526</a></td>
<td valign="top">Silicon Dioxide Deposition Methods Using at Least Ozone and TEOS as Deposition Precursors</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120015524.PGNR.&#038;OS=DN/20120015524RS=DN/20120015524" target="_blank">20120015524</a></td>
<td valign="top">Process for Enhancing Solubility and Reaction Rates In Supercritical Fluids</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120014185.PGNR.&#038;OS=DN/20120014185RS=DN/20120014185" target="_blank">20120014185</a></td>
<td valign="top">CIRCUITS, SYSTEMS AND METHODS FOR DRIVING HIGH AND LOW VOLTAGES ON BIT LINES IN NON-VOLATILE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120014166.PGNR.&#038;OS=DN/20120014166RS=DN/20120014166" target="_blank">20120014166</a></td>
<td valign="top">RESISTIVE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120013368.PGNR.&#038;OS=DN/20120013368RS=DN/20120013368" target="_blank">20120013368</a></td>
<td valign="top">METHOD AND SYSTEM FOR ELECTRICALLY COUPLING A CHIP TO CHIP PACKAGE</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120013314.PGNR.&#038;OS=DN/20120013314RS=DN/20120013314" target="_blank">20120013314</a></td>
<td valign="top">VOLTAGE REGULATOR SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120013273.PGNR.&#038;OS=DN/20120013273RS=DN/20120013273" target="_blank">20120013273</a></td>
<td valign="top">SOLID STATE LIGHTING DEVICES WITHOUT CONVERTER MATERIALS AND ASSOCIATED METHODS OF MANUFACTURING</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120012921.PGNR.&#038;OS=DN/20120012921RS=DN/20120012921" target="_blank">20120012921</a></td>
<td valign="top">MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120012914.PGNR.&#038;OS=DN/20120012914RS=DN/20120012914" target="_blank">20120012914</a></td>
<td valign="top">Semiconductor Constructions, and Methods of Forming Semiconductor Constructions</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120012855.PGNR.&#038;OS=DN/20120012855RS=DN/20120012855" target="_blank">20120012855</a></td>
<td valign="top">SOLID-STATE LIGHT EMITTERS HAVING SUBSTRATES WITH THERMAL AND ELECTRICAL CONDUCTIVITY ENHANCEMENTS AND METHOD OF MANUFACTURE</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120012812.PGNR.&#038;OS=DN/20120012812RS=DN/20120012812" target="_blank">20120012812</a></td>
<td valign="top">SOLID STATE LIGHTING DEVICES WITH REDUCED CRYSTAL LATTICE DISLOCATIONS AND ASSOCIATED METHODS OF MANUFACTURING</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 17 January 2012</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-17-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-17-january-2012/#comments</comments>
		<pubDate>Wed, 18 Jan 2012 00:34:52 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16196</guid>
		<description><![CDATA[11 US patents granted on 17 January 2012 and assigned to Micron 1 8,099,543 Methods of operarting memory devices within a communication protocol standard timeout requirement 2 8,099,366 Software distribution method and apparatus 3 8,098,530 Systems and methods for erasing a memory 4 8,098,529 Memory device having buried boosting plate and methods of operating the [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patents granted on 17 January 2012 and assigned to Micron<br />
<span id="more-16196"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,099,543" target="_blank" rel="nofollow">8,099,543</a></td>
<td valign="top">Methods of operarting memory devices within a communication protocol standard timeout requirement</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,099,366" target="_blank" rel="nofollow">8,099,366</a></td>
<td valign="top">Software distribution method and apparatus</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,098,530" target="_blank" rel="nofollow">8,098,530</a></td>
<td valign="top">Systems and methods for erasing a memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,098,529" target="_blank" rel="nofollow">8,098,529</a></td>
<td valign="top">Memory device having buried boosting plate and methods of operating the same</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,098,180" target="_blank" rel="nofollow">8,098,180</a></td>
<td valign="top">Devices including analog-to-digital converters for internal data storage locations</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,947" target="_blank" rel="nofollow">8,097,947</a></td>
<td valign="top">Conductive systems and devices including wires coupled to anisotropic conductive film, and methods of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,910" target="_blank" rel="nofollow">8,097,910</a></td>
<td valign="top">Vertical transistors</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,908" target="_blank" rel="nofollow">8,097,908</a></td>
<td valign="top">Antiblooming imaging apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,537" target="_blank" rel="nofollow">8,097,537</a></td>
<td valign="top">Phase change memory cell structures and methods</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,506" target="_blank" rel="nofollow">8,097,506</a></td>
<td valign="top">Shallow trench isolation for a memory</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,097,175" target="_blank" rel="nofollow">8,097,175</a></td>
<td valign="top">Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 12 January 2012</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-12-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-12-january-2012/#comments</comments>
		<pubDate>Thu, 12 Jan 2012 22:11:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16156</guid>
		<description><![CDATA[12 US patent applications published on 12 January 2012 and assigned to Micron 1 20120011409 DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY 2 20120011335 MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS 3 20120009793 METHOD FOR SELECTIVELY MODIFYING SPACING BETWEEN PITCH MULTIPLIED [...]]]></description>
			<content:encoded><![CDATA[<p>12 US patent applications published on 12 January 2012 and assigned to Micron<br />
<span id="more-16156"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120011409.PGNR.&#038;OS=DN/20120011409RS=DN/20120011409" target="_blank">20120011409</a></td>
<td valign="top">DEVICES, METHODS, AND APPARATUSES FOR DETECTION, SENSING, AND REPORTING FUNCTIONALITY FOR SEMICONDUCTOR MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120011335.PGNR.&#038;OS=DN/20120011335RS=DN/20120011335" target="_blank">20120011335</a></td>
<td valign="top">MEMORY CONTROLLERS, MEMORY SYSTEMS, SOLID STATE DRIVES AND METHODS FOR PROCESSING A NUMBER OF COMMANDS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120009793.PGNR.&#038;OS=DN/20120009793RS=DN/20120009793" target="_blank">20120009793</a></td>
<td valign="top">METHOD FOR SELECTIVELY MODIFYING SPACING BETWEEN PITCH MULTIPLIED STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120009779.PGNR.&#038;OS=DN/20120009779RS=DN/20120009779" target="_blank">20120009779</a></td>
<td valign="top">CONTACT FORMATION</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120009776.PGNR.&#038;OS=DN/20120009776RS=DN/20120009776" target="_blank">20120009776</a></td>
<td valign="top">SEMICONDUCTOR SUBSTRATES WITH UNITARY VIAS AND VIA TERMINALS, AND ASSOCIATED SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120008440.PGNR.&#038;OS=DN/20120008440RS=DN/20120008440" target="_blank">20120008440</a></td>
<td valign="top">DATA RETENTION KILL FUNCTION</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120008409.PGNR.&#038;OS=DN/20120008409RS=DN/20120008409" target="_blank">20120008409</a></td>
<td valign="top">REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120008404.PGNR.&#038;OS=DN/20120008404RS=DN/20120008404" target="_blank">20120008404</a></td>
<td valign="top">SYSTEM AND METHOD FOR REDUCING PIN-COUNT OF MEMORY DEVICES, AND MEMORY DEVICE TESTERS FOR SAME</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120008399.PGNR.&#038;OS=DN/20120008399RS=DN/20120008399" target="_blank">20120008399</a></td>
<td valign="top">METHODS OF OPERATING MEMORIES INCLUDING CHARACTERIZING MEMORY CELL SIGNAL LINES</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120007256.PGNR.&#038;OS=DN/20120007256RS=DN/20120007256" target="_blank">20120007256</a></td>
<td valign="top">REDISTRIBUTION LAYERS FOR MICROFEATURE WORKPIECES, AND ASSOCIATED SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120007209.PGNR.&#038;OS=DN/20120007209RS=DN/20120007209" target="_blank">20120007209</a></td>
<td valign="top">SEMICONDUCTOR DEVICE STRUCTURES INCLUDING DAMASCENE TRENCHES WITH CONDUCTIVE STRUCTURES AND RELATED METHOD</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120007037.PGNR.&#038;OS=DN/20120007037RS=DN/20120007037" target="_blank">20120007037</a></td>
<td valign="top">CROSS-POINT MEMORY UTILIZING Ru/Si DIODE</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 10 January 2012</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-10-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-10-january-2012/#comments</comments>
		<pubDate>Tue, 10 Jan 2012 23:55:46 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16116</guid>
		<description><![CDATA[21 US patents granted on 10 January 2012 and assigned to Micron 1 8,095,835 Error scanning in flash memory 2 8,095,834 Macro and command execution from memory array 3 8,095,765 Memory block management 4 8,095,748 Method and apparatus for sending data from multiple sources over a communications bus 5 8,094,984 Semiconductor constructions, methods of forming [...]]]></description>
			<content:encoded><![CDATA[<p>21 US patents granted on 10 January 2012 and assigned to Micron<br />
<span id="more-16116"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,095,835" target="_blank" rel="nofollow">8,095,835</a></td>
<td valign="top">Error scanning in flash memory</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,095,834" target="_blank" rel="nofollow">8,095,834</a></td>
<td valign="top">Macro and command execution from memory array</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,095,765" target="_blank" rel="nofollow">8,095,765</a></td>
<td valign="top">Memory block management</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,095,748" target="_blank" rel="nofollow">8,095,748</a></td>
<td valign="top">Method and apparatus for sending data from multiple sources over a communications bus</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,094,984" target="_blank" rel="nofollow">8,094,984</a></td>
<td valign="top">Semiconductor constructions, methods of forming semiconductor constructions, light-conducting conduits, and optical signal propagation assemblies</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,094,508" target="_blank" rel="nofollow">8,094,508</a></td>
<td valign="top">Memory block testing</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,094,507" target="_blank" rel="nofollow">8,094,507</a></td>
<td valign="top">Command latency systems and methods</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,094,047" target="_blank" rel="nofollow">8,094,047</a></td>
<td valign="top">Data serializer apparatus and methods</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,094,045" target="_blank" rel="nofollow">8,094,045</a></td>
<td valign="top">Data bus inversion apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,937" target="_blank" rel="nofollow">8,093,937</a></td>
<td valign="top">Seamless coarse and fine delay structure for high performance DLL</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,730" target="_blank" rel="nofollow">8,093,730</a></td>
<td valign="top">Underfilled semiconductor die assemblies and methods of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,725" target="_blank" rel="nofollow">8,093,725</a></td>
<td valign="top">High aspect ratio contacts</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,702" target="_blank" rel="nofollow">8,093,702</a></td>
<td valign="top">Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,666" target="_blank" rel="nofollow">8,093,666</a></td>
<td valign="top">Lanthanide yttrium aluminum oxide dielectric films</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,658" target="_blank" rel="nofollow">8,093,658</a></td>
<td valign="top">Electronic device with asymmetric gate strain</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,643" target="_blank" rel="nofollow">8,093,643</a></td>
<td valign="top">Multi-resistive integrated circuit memory</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,638" target="_blank" rel="nofollow">8,093,638</a></td>
<td valign="top">Systems with a gate dielectric having multiple lanthanide oxide layers</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,576" target="_blank" rel="nofollow">8,093,576</a></td>
<td valign="top">Chemical-mechanical polish termination layer to build electrical device isolation</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,155" target="_blank" rel="nofollow">8,093,155</a></td>
<td valign="top">Method of controlling striations and CD loss in contact oxide etch</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,129" target="_blank" rel="nofollow">8,093,129</a></td>
<td valign="top">Methods of forming memory cells</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,093,090" target="_blank" rel="nofollow">8,093,090</a></td>
<td valign="top">Integrated circuit edge and method to fabricate the same</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 05 January 2012</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-05-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-05-january-2012/#comments</comments>
		<pubDate>Thu, 05 Jan 2012 18:47:08 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16076</guid>
		<description><![CDATA[18 US patent applications published on 05 January 2012 and assigned to Micron 1 20120005411 NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY 2 20120003810 SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE 3 20120003573 Photomasks 4 20120002489 SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL 5 20120002477 MEMORIES AND THEIR FORMATION 6 [...]]]></description>
			<content:encoded><![CDATA[<p>18 US patent applications published on 05 January 2012 and assigned to Micron<br />
<span id="more-16076"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120005411.PGNR.&#038;OS=DN/20120005411RS=DN/20120005411" target="_blank">20120005411</a></td>
<td valign="top">NON-VOLATILE CONFIGURATION FOR SERIAL NON-VOLATILE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120003810.PGNR.&#038;OS=DN/20120003810RS=DN/20120003810" target="_blank">20120003810</a></td>
<td valign="top">SEMICONDUCTOR DEVICE HAVING REDUCED SUB-THRESHOLD LEAKAGE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120003573.PGNR.&#038;OS=DN/20120003573RS=DN/20120003573" target="_blank">20120003573</a></td>
<td valign="top">Photomasks</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120002489.PGNR.&#038;OS=DN/20120002489RS=DN/20120002489" target="_blank">20120002489</a></td>
<td valign="top">SIGNAL DRIVER CIRCUIT HAVING ADJUSTABLE OUTPUT VOLTAGE FOR A HIGH LOGIC LEVEL OUTPUT SIGNAL</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120002477.PGNR.&#038;OS=DN/20120002477RS=DN/20120002477" target="_blank">20120002477</a></td>
<td valign="top">MEMORIES AND THEIR FORMATION</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120002468.PGNR.&#038;OS=DN/20120002468RS=DN/20120002468" target="_blank">20120002468</a></td>
<td valign="top">CELL DETERIORATION WARNING APPARATUS AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120002467.PGNR.&#038;OS=DN/20120002467RS=DN/20120002467" target="_blank">20120002467</a></td>
<td valign="top">SINGLE TRANSISTOR MEMORY CELL</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120002465.PGNR.&#038;OS=DN/20120002465RS=DN/20120002465" target="_blank">20120002465</a></td>
<td valign="top">METHODS, STRUCTURES, AND DEVICES FOR REDUCING OPERATIONAL ENERGY IN PHASE CHANGE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001682.PGNR.&#038;OS=DN/20120001682RS=DN/20120001682" target="_blank">20120001682</a></td>
<td valign="top">APPARATUSES AND METHODS TO REDUCE POWER CONSUMPTION IN DIGITAL CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001680.PGNR.&#038;OS=DN/20120001680RS=DN/20120001680" target="_blank">20120001680</a></td>
<td valign="top">ISOLATION CIRCUIT</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001539.PGNR.&#038;OS=DN/20120001539RS=DN/20120001539" target="_blank">20120001539</a></td>
<td valign="top">Plasma-Generating Structures, Display Devices, and Methods of Forming Plasma-Generating Structures</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001299.PGNR.&#038;OS=DN/20120001299RS=DN/20120001299" target="_blank">20120001299</a></td>
<td valign="top">Semiconductor Constructions</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001253.PGNR.&#038;OS=DN/20120001253RS=DN/20120001253" target="_blank">20120001253</a></td>
<td valign="top">FLATBAND VOLTAGE ADJUSTMENT IN A SEMICONDUCTOR DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001248.PGNR.&#038;OS=DN/20120001248RS=DN/20120001248" target="_blank">20120001248</a></td>
<td valign="top">METHODS OF FORMING NANOSCALE FLOATING GATE</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001246.PGNR.&#038;OS=DN/20120001246RS=DN/20120001246" target="_blank">20120001246</a></td>
<td valign="top">MEMORY DEVICE AND METHOD OF FABRICATING THEREOF</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001245.PGNR.&#038;OS=DN/20120001245RS=DN/20120001245" target="_blank">20120001245</a></td>
<td valign="top">Recessed Access Device for a Memory</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001147.PGNR.&#038;OS=DN/20120001147RS=DN/20120001147" target="_blank">20120001147</a></td>
<td valign="top">Non-Volatile Resistive Oxide Memory Cells, Non-Volatile Resistive Oxide Memory Arrays, And Methods Of Forming Non-Volatile Resistive Oxide Memory Cells And Memory Arrays</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20120001144.PGNR.&#038;OS=DN/20120001144RS=DN/20120001144" target="_blank">20120001144</a></td>
<td valign="top">RESISTIVE RAM DEVICES AND METHODS</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 03 January 2012</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-03-january-2012/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-03-january-2012/#comments</comments>
		<pubDate>Tue, 03 Jan 2012 13:49:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=16036</guid>
		<description><![CDATA[16 US patents granted on 03 January 2012 and assigned to Micron 1 8,090,999 Memory media characterization for development of signal processors 2 8,090,955 Boot block features in synchronous serial interface NAND 3 8,090,886 Direct secondary device interface by a host 4 8,089,816 Memory erase methods and devices 5 8,089,805 Two-part programming methods and memories [...]]]></description>
			<content:encoded><![CDATA[<p>16 US patents granted on 03 January 2012 and assigned to Micron<br />
<span id="more-16036"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,090,999" target="_blank" rel="nofollow">8,090,999</a></td>
<td valign="top">Memory media characterization for development of signal processors</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,090,955" target="_blank" rel="nofollow">8,090,955</a></td>
<td valign="top">Boot block features in synchronous serial interface NAND</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,090,886" target="_blank" rel="nofollow">8,090,886</a></td>
<td valign="top">Direct secondary device interface by a host</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,816" target="_blank" rel="nofollow">8,089,816</a></td>
<td valign="top">Memory erase methods and devices</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,805" target="_blank" rel="nofollow">8,089,805</a></td>
<td valign="top">Two-part programming methods and memories</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,800" target="_blank" rel="nofollow">8,089,800</a></td>
<td valign="top">Memory cell</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,542" target="_blank" rel="nofollow">8,089,542</a></td>
<td valign="top">CMOS imager with integrated circuitry</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,387" target="_blank" rel="nofollow">8,089,387</a></td>
<td valign="top">Quantizing circuits with variable parameters</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,142" target="_blank" rel="nofollow">8,089,142</a></td>
<td valign="top">Methods and apparatus for a stacked-die interposer</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,128" target="_blank" rel="nofollow">8,089,128</a></td>
<td valign="top">Transistor gate forming methods and integrated circuits</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,089,123" target="_blank" rel="nofollow">8,089,123</a></td>
<td valign="top">Semiconductor device comprising transistor structures and methods for forming same</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,088,691" target="_blank" rel="nofollow">8,088,691</a></td>
<td valign="top">Selective etch chemistries for forming high aspect ratio features and associated structures</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,088,659" target="_blank" rel="nofollow">8,088,659</a></td>
<td valign="top">Method of forming capacitors</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,088,643" target="_blank" rel="nofollow">8,088,643</a></td>
<td valign="top">Resistance variable memory device with nanoparticle electrode and method of fabrication</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,088,551" target="_blank" rel="nofollow">8,088,551</a></td>
<td valign="top">Methods of utilizing block copolymer to form patterns</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,088,293" target="_blank" rel="nofollow">8,088,293</a></td>
<td valign="top">Methods of forming reticles configured for imprint lithography</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 29 December 2011</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-29-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-29-december-2011/#comments</comments>
		<pubDate>Thu, 29 Dec 2011 22:17:29 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15994</guid>
		<description><![CDATA[16 US patent applications published on 29 December 2011 and assigned to Micron 1 20110318921 Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM 2 20110318899 Methods of Forming Capacitors 3 20110317509 MEMORY DEVICE WORD LINE DRIVERS AND METHODS 4 20110317502 CONTROL OF INPUTS TO A MEMORY [...]]]></description>
			<content:encoded><![CDATA[<p>16 US patent applications published on 29 December 2011 and assigned to Micron<br />
<span id="more-15994"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110318921.PGNR.&#038;OS=DN/20110318921RS=DN/20110318921" target="_blank">20110318921</a></td>
<td valign="top">Methods Of Forming An Interconnect Between A Substrate Bit Line Contact And A Bit Line In DRAM</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110318899.PGNR.&#038;OS=DN/20110318899RS=DN/20110318899" target="_blank">20110318899</a></td>
<td valign="top">Methods of Forming Capacitors</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110317509.PGNR.&#038;OS=DN/20110317509RS=DN/20110317509" target="_blank">20110317509</a></td>
<td valign="top">MEMORY DEVICE WORD LINE DRIVERS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110317502.PGNR.&#038;OS=DN/20110317502RS=DN/20110317502" target="_blank">20110317502</a></td>
<td valign="top">CONTROL OF INPUTS TO A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110317473.PGNR.&#038;OS=DN/20110317473RS=DN/20110317473" target="_blank">20110317473</a></td>
<td valign="top">SYSTEM AND METHOD FOR MITIGATING REVERSE BIAS LEAKAGE</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110317046.PGNR.&#038;OS=DN/20110317046RS=DN/20110317046" target="_blank">20110317046</a></td>
<td valign="top">MISSING PIXEL ARRAY</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316726.PGNR.&#038;OS=DN/20110316726RS=DN/20110316726" target="_blank">20110316726</a></td>
<td valign="top">LOW POWER MULTI-LEVEL SIGNALING</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316599.PGNR.&#038;OS=DN/20110316599RS=DN/20110316599" target="_blank">20110316599</a></td>
<td valign="top">MULTI-PHASE CLOCK GENERATION</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316512.PGNR.&#038;OS=DN/20110316512RS=DN/20110316512" target="_blank">20110316512</a></td>
<td valign="top">VOLTAGE TRIMMING</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316125.PGNR.&#038;OS=DN/20110316125RS=DN/20110316125" target="_blank">20110316125</a></td>
<td valign="top">INTERMEDIATE STRUCTURES FOR FORMING CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316114.PGNR.&#038;OS=DN/20110316114RS=DN/20110316114" target="_blank">20110316114</a></td>
<td valign="top">SIMPLIFIED PITCH DOUBLING PROCESS FLOW</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316091.PGNR.&#038;OS=DN/20110316091RS=DN/20110316091" target="_blank">20110316091</a></td>
<td valign="top">Semiconductor Devices, Assemblies And Constructions</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316068.PGNR.&#038;OS=DN/20110316068RS=DN/20110316068" target="_blank">20110316068</a></td>
<td valign="top">FLASH MEMORY WITH RECESSED FLOATING GATE</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110316042.PGNR.&#038;OS=DN/20110316042RS=DN/20110316042" target="_blank">20110316042</a></td>
<td valign="top">THYRISTOR RANDOM ACCESS MEMORY DEVICE AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110315944.PGNR.&#038;OS=DN/20110315944RS=DN/20110315944" target="_blank">20110315944</a></td>
<td valign="top">RESISTIVE MEMORY AND METHODS OF PROCESSING RESISTIVE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110315543.PGNR.&#038;OS=DN/20110315543RS=DN/20110315543" target="_blank">20110315543</a></td>
<td valign="top">FORMING MEMORY USING HIGH POWER IMPULSE MAGNETRON SPUTTERING</td>
</tr>
</table>
]]></content:encoded>
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		<item>
		<title>Micron patents granted on 27 December 2011</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-27-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-27-december-2011/#comments</comments>
		<pubDate>Tue, 27 Dec 2011 15:25:35 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15954</guid>
		<description><![CDATA[24 US patents granted on 27 December 2011 and assigned to Micron 1 8,086,920 Method of controlling a test mode of a circuit 2 8,086,916 System and method for running test and redundancy analysis in parallel 3 8,086,913 Methods, apparatus, and systems to repair memory 4 8,086,790 Non-volatile memory device having assignable network identification 5 [...]]]></description>
			<content:encoded><![CDATA[<p>24 US patents granted on 27 December 2011 and assigned to Micron<br />
<span id="more-15954"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,086,920" target="_blank" rel="nofollow">8,086,920</a></td>
<td valign="top">Method of controlling a test mode of a circuit</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,086,916" target="_blank" rel="nofollow">8,086,916</a></td>
<td valign="top">System and method for running test and redundancy analysis in parallel</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,086,913" target="_blank" rel="nofollow">8,086,913</a></td>
<td valign="top">Methods, apparatus, and systems to repair memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,086,790" target="_blank" rel="nofollow">8,086,790</a></td>
<td valign="top">Non-volatile memory device having assignable network identification</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,612" target="_blank" rel="nofollow">8,085,612</a></td>
<td valign="top">Method and apparatus for managing behavior of memory devices</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,606" target="_blank" rel="nofollow">8,085,606</a></td>
<td valign="top">Input-output line sense amplifier having adjustable output drive capability</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,596" target="_blank" rel="nofollow">8,085,596</a></td>
<td valign="top">Reducing noise in semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,594" target="_blank" rel="nofollow">8,085,594</a></td>
<td valign="top">Reading technique for memory cell with electrically floating body transistor</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,591" target="_blank" rel="nofollow">8,085,591</a></td>
<td valign="top">Charge loss compensation during programming of a memory device</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,085,584" target="_blank" rel="nofollow">8,085,584</a></td>
<td valign="top">Memory to store user-configurable data polarity</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,866" target="_blank" rel="nofollow">8,084,866</a></td>
<td valign="top">Microelectronic devices and methods for filling vias in microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,854" target="_blank" rel="nofollow">8,084,854</a></td>
<td valign="top">Pass-through 3D interconnect for microelectronic dies and associated systems and methods</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,846" target="_blank" rel="nofollow">8,084,846</a></td>
<td valign="top">Balanced semiconductor device packages including lead frame with floating leads and associated methods</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,845" target="_blank" rel="nofollow">8,084,845</a></td>
<td valign="top">Subresolution silicon features and methods for forming the same</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,843" target="_blank" rel="nofollow">8,084,843</a></td>
<td valign="top">N well implants to separate blocks in a flash memory device</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,808" target="_blank" rel="nofollow">8,084,808</a></td>
<td valign="top">Zirconium silicon oxide films</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,806" target="_blank" rel="nofollow">8,084,806</a></td>
<td valign="top">Isolation structure for a memory cell using A1.sub.2O.sub.3 dielectric</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,370" target="_blank" rel="nofollow">8,084,370</a></td>
<td valign="top">Hafnium tantalum oxynitride dielectric</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,355" target="_blank" rel="nofollow">8,084,355</a></td>
<td valign="top">Methods of forming copper-comprising conductive lines in the fabrication of integrated circuitry</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,345" target="_blank" rel="nofollow">8,084,345</a></td>
<td valign="top">Methods of forming dispersions of nanoparticles, and methods of forming flash memory cells</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,322" target="_blank" rel="nofollow">8,084,322</a></td>
<td valign="top">Method of manufacturing devices having vertical junction edge</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,296" target="_blank" rel="nofollow">8,084,296</a></td>
<td valign="top">Methods for reducing stress in microelectronic devices and microelectronic devices formed using such methods</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,084,142" target="_blank" rel="nofollow">8,084,142</a></td>
<td valign="top">Methods of forming conductive contacts to source/drain regions and methods of forming local interconnects</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,083,953" target="_blank" rel="nofollow">8,083,953</a></td>
<td valign="top">Registered structure formation via the application of directed thermal energy to diblock copolymer films</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 22 December 2011</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-22-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-22-december-2011/#comments</comments>
		<pubDate>Fri, 23 Dec 2011 01:54:59 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15910</guid>
		<description><![CDATA[11 US patent applications published on 22 December 2011 and assigned to Micron 1 20110314215 MULTI-PRIORITY ENCODER 2 20110310689 POWER SOURCE AND POWER SOURCE CONTROL CIRCUIT 3 20110310687 CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS 4 20110310683 NON-VOLATILE MEMORY CONTROL 5 20110310679 DEVICES, SYSTEMS, AND METHODS FOR A POWER GENERATOR SYSTEM 6 20110310675 LOCAL SENSING [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patent applications published on 22 December 2011 and assigned to Micron<br />
<span id="more-15910"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110314215.PGNR.&#038;OS=DN/20110314215RS=DN/20110314215" target="_blank">20110314215</a></td>
<td valign="top">MULTI-PRIORITY ENCODER</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310689.PGNR.&#038;OS=DN/20110310689RS=DN/20110310689" target="_blank">20110310689</a></td>
<td valign="top">POWER SOURCE AND POWER SOURCE CONTROL CIRCUIT</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310687.PGNR.&#038;OS=DN/20110310687RS=DN/20110310687" target="_blank">20110310687</a></td>
<td valign="top">CURRENT SENSE AMPLIFIERS, MEMORY DEVICES AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310683.PGNR.&#038;OS=DN/20110310683RS=DN/20110310683" target="_blank">20110310683</a></td>
<td valign="top">NON-VOLATILE MEMORY CONTROL</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310679.PGNR.&#038;OS=DN/20110310679RS=DN/20110310679" target="_blank">20110310679</a></td>
<td valign="top">DEVICES, SYSTEMS, AND METHODS FOR A POWER GENERATOR SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310675.PGNR.&#038;OS=DN/20110310675RS=DN/20110310675" target="_blank">20110310675</a></td>
<td valign="top">LOCAL SENSING IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110310661.PGNR.&#038;OS=DN/20110310661RS=DN/20110310661" target="_blank">20110310661</a></td>
<td valign="top">MEMORY SENSING DEVICES, METHODS, AND SYSTEMS</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110309506.PGNR.&#038;OS=DN/20110309506RS=DN/20110309506" target="_blank">20110309506</a></td>
<td valign="top">CONDUCTIVE INTERCONNECT STRUCTURES AND FORMATION METHODS USING SUPERCRITICAL FLUIDS</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110309393.PGNR.&#038;OS=DN/20110309393RS=DN/20110309393" target="_blank">20110309393</a></td>
<td valign="top">PACKAGED LEDS WITH PHOSPHOR FILMS, AND ASSOCIATED SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110309324.PGNR.&#038;OS=DN/20110309324RS=DN/20110309324" target="_blank">20110309324</a></td>
<td valign="top">SOLID STATE DEVICES WITH SEMI-POLAR FACETS AND ASSOCIATED METHODS OF MANUFACTURING</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110309319.PGNR.&#038;OS=DN/20110309319RS=DN/20110309319" target="_blank">20110309319</a></td>
<td valign="top">HORIZONTALLY ORIENTED AND VERTICALLY STACKED MEMORY CELLS</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 20 December 2011</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-20-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-20-december-2011/#comments</comments>
		<pubDate>Wed, 21 Dec 2011 03:59:10 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15869</guid>
		<description><![CDATA[14 US patents granted on 20 December 2011 and assigned to Micron 1 8,082,456 Data controlled power supply apparatus 2 8,082,435 Memory device initiate and terminate boot commands 3 8,082,413 Detection circuit for mixed asynchronous and synchronous memory operation 4 8,082,404 Memory arbitration system and method having an arbitration packet protocol 5 8,082,387 Methods, systems, [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patents granted on 20 December 2011 and assigned to Micron<br />
<span id="more-15869"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,456" target="_blank" rel="nofollow">8,082,456</a></td>
<td valign="top">Data controlled power supply apparatus</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,435" target="_blank" rel="nofollow">8,082,435</a></td>
<td valign="top">Memory device initiate and terminate boot commands</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,413" target="_blank" rel="nofollow">8,082,413</a></td>
<td valign="top">Detection circuit for mixed asynchronous and synchronous memory operation</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,404" target="_blank" rel="nofollow">8,082,404</a></td>
<td valign="top">Memory arbitration system and method having an arbitration packet protocol</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,387" target="_blank" rel="nofollow">8,082,387</a></td>
<td valign="top">Methods, systems, and devices for management of a memory system</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,082,382" target="_blank" rel="nofollow">8,082,382</a></td>
<td valign="top">Memory device with user configurable density/performance</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,081,511" target="_blank" rel="nofollow">8,081,511</a></td>
<td valign="top">Flash memory device with redundant columns</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,081,249" target="_blank" rel="nofollow">8,081,249</a></td>
<td valign="top">Image sensor with a gated storage node linked to transfer gate</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,081,020" target="_blank" rel="nofollow">8,081,020</a></td>
<td valign="top">Delay-lock loop and method adapting itself to operate over a wide frequency range</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,080,837" target="_blank" rel="nofollow">8,080,837</a></td>
<td valign="top">Memory devices, transistors, and memory cells</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,080,817" target="_blank" rel="nofollow">8,080,817</a></td>
<td valign="top">Memory cells</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,080,816" target="_blank" rel="nofollow">8,080,816</a></td>
<td valign="top">Silver-selenide/chalcogenide glass stack for resistance variable memory</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,080,615" target="_blank" rel="nofollow">8,080,615</a></td>
<td valign="top">Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,080,460" target="_blank" rel="nofollow">8,080,460</a></td>
<td valign="top">Methods of forming diodes</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 15 December 2011</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-15-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-15-december-2011/#comments</comments>
		<pubDate>Fri, 16 Dec 2011 04:36:45 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15827</guid>
		<description><![CDATA[6 US patent applications published on 15 December 2011 and assigned to Micron 1 20110307682 BLOCK MANAGEMENT FOR MASS STORAGE 2 20110305090 MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE 3 20110305021 SOLID STATE LIGHTING DEVICE WITH DIFFERENT ILLUMINATION PARAMETERS AT DIFFERENT REGIONS OF AN EMITTER ARRAY 4 20110304358 TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS [...]]]></description>
			<content:encoded><![CDATA[<p>6 US patent applications published on 15 December 2011 and assigned to Micron<br />
<span id="more-15827"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110307682.PGNR.&#038;OS=DN/20110307682RS=DN/20110307682" target="_blank">20110307682</a></td>
<td valign="top">BLOCK MANAGEMENT FOR MASS STORAGE</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110305090.PGNR.&#038;OS=DN/20110305090RS=DN/20110305090" target="_blank">20110305090</a></td>
<td valign="top">MEMORY CONTROLLER SELF-CALIBRATION FOR REMOVING SYSTEMIC INFLUENCE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110305021.PGNR.&#038;OS=DN/20110305021RS=DN/20110305021" target="_blank">20110305021</a></td>
<td valign="top">SOLID STATE LIGHTING DEVICE WITH DIFFERENT ILLUMINATION PARAMETERS AT DIFFERENT REGIONS OF AN EMITTER ARRAY</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110304358.PGNR.&#038;OS=DN/20110304358RS=DN/20110304358" target="_blank">20110304358</a></td>
<td valign="top">TRANSISTOR VOLTAGE THRESHOLD MISMATCH COMPENSATED SENSE AMPLIFIERS AND METHODS FOR PRECHARGING SENSE AMPLIFIERS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110303957.PGNR.&#038;OS=DN/20110303957RS=DN/20110303957" target="_blank">20110303957</a></td>
<td valign="top">Concentric or Nested Container Capacitor Structure for Integrated Circuits</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110303929.PGNR.&#038;OS=DN/20110303929RS=DN/20110303929" target="_blank">20110303929</a></td>
<td valign="top">MULTI-DIMENSIONAL LED ARRAY SYSTEM AND ASSOCIATED METHODS AND STRUCTURES</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 13 December 2011</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-13-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-13-december-2011/#comments</comments>
		<pubDate>Wed, 14 Dec 2011 00:11:51 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15786</guid>
		<description><![CDATA[25 US patents granted on 13 December 2011 and assigned to Micron 1 8,078,848 Memory controller having front end and back end channels for modifying commands 2 8,078,797 Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices 3 8,078,796 Method for writing to and erasing a non-volatile [...]]]></description>
			<content:encoded><![CDATA[<p>25 US patents granted on 13 December 2011 and assigned to Micron<br />
<span id="more-15786"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,078,848" target="_blank" rel="nofollow">8,078,848</a></td>
<td valign="top">Memory controller having front end and back end channels for modifying commands</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,078,797" target="_blank" rel="nofollow">8,078,797</a></td>
<td valign="top">Increasing the memory performance of flash memory devices by writing sectors simultaneously to multiple flash memory devices</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,078,796" target="_blank" rel="nofollow">8,078,796</a></td>
<td valign="top">Method for writing to and erasing a non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,078,018" target="_blank" rel="nofollow">8,078,018</a></td>
<td valign="top">Communication methods, methods of forming an interconnect, signal interconnects, integrated circuit structures, circuits, and data apparatuses</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,078,001" target="_blank" rel="nofollow">8,078,001</a></td>
<td valign="top">Methods, apparatuses and systems for piecewise generation of pixel correction values for image processing</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,077,538" target="_blank" rel="nofollow">8,077,538</a></td>
<td valign="top">Address decoder and/or access line driver and method for memory devices</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,077,532" target="_blank" rel="nofollow">8,077,532</a></td>
<td valign="top">Small unit internal verify read in a memory device</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,077,519" target="_blank" rel="nofollow">8,077,519</a></td>
<td valign="top">Programming a memory device to increase data reliability</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,077,515" target="_blank" rel="nofollow">8,077,515</a></td>
<td valign="top">Methods, devices, and systems for dealing with threshold voltage change in memory devices</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,760" target="_blank" rel="nofollow">8,076,760</a></td>
<td valign="top">Semiconductor fuse arrangements</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,727" target="_blank" rel="nofollow">8,076,727</a></td>
<td valign="top">Magnesium-doped zinc oxide structures and methods</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,721" target="_blank" rel="nofollow">8,076,721</a></td>
<td valign="top">Fin structures and methods of fabricating fin structures</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,717" target="_blank" rel="nofollow">8,076,717</a></td>
<td valign="top">Vertically-oriented semiconductor selection device for cross-point array memory</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,714" target="_blank" rel="nofollow">8,076,714</a></td>
<td valign="top">Memory device with high dielectric constant gate dielectrics and metal floating gates</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,673" target="_blank" rel="nofollow">8,076,673</a></td>
<td valign="top">Recessed gate dielectric antifuse</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,663" target="_blank" rel="nofollow">8,076,663</a></td>
<td valign="top">Phase change memory structures</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,249" target="_blank" rel="nofollow">8,076,249</a></td>
<td valign="top">Structures containing titanium silicon oxide</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,248" target="_blank" rel="nofollow">8,076,248</a></td>
<td valign="top">Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,244" target="_blank" rel="nofollow">8,076,244</a></td>
<td valign="top">Methods for causing fluid to flow through or into via holes, vents and other openings or recesses that communicate with surfaces of substrates of semiconductor device components</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,229" target="_blank" rel="nofollow">8,076,229</a></td>
<td valign="top">Methods of forming data cells and connections to data cells</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,211" target="_blank" rel="nofollow">8,076,211</a></td>
<td valign="top">Fabricating bipolar junction select transistors for semiconductor memories</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,208" target="_blank" rel="nofollow">8,076,208</a></td>
<td valign="top">Method for forming transistor with high breakdown voltage using pitch multiplication technique</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,200" target="_blank" rel="nofollow">8,076,200</a></td>
<td valign="top">Charge trapping dielectric structures with variable band-gaps</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,076,195" target="_blank" rel="nofollow">8,076,195</a></td>
<td valign="top">Resistive memory architectures with multiple memory cells per access device</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,074,353" target="_blank" rel="nofollow">8,074,353</a></td>
<td valign="top">Methods of providing semiconductor components within sockets</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 08 December 2011</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-08-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-08-december-2011/#comments</comments>
		<pubDate>Fri, 09 Dec 2011 01:31:06 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15744</guid>
		<description><![CDATA[12 US patent applications published on 08 December 2011 and assigned to Micron 1 20110302470 TEST MODE FOR PARALLEL LOAD OF ADDRESS DEPENDENT DATA TO ENABLE LOADING OF DESIRED DATA BACKGROUNDS 2 20110301383 Beta-Diketiminate Ligand Sources and Metal-Containing Compounds Thereof, and Systems and Methods Including Same 3 20110300782 APPARATUSES AND METHODS FOR CONDITIONING POLISHING PADS [...]]]></description>
			<content:encoded><![CDATA[<p>12 US patent applications published on 08 December 2011 and assigned to Micron<br />
<span id="more-15744"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110302470.PGNR.&#038;OS=DN/20110302470RS=DN/20110302470" target="_blank">20110302470</a></td>
<td valign="top">TEST MODE FOR PARALLEL LOAD OF ADDRESS DEPENDENT DATA TO ENABLE LOADING OF DESIRED DATA BACKGROUNDS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110301383.PGNR.&#038;OS=DN/20110301383RS=DN/20110301383" target="_blank">20110301383</a></td>
<td valign="top">Beta-Diketiminate Ligand Sources and Metal-Containing Compounds Thereof, and Systems and Methods Including Same</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110300782.PGNR.&#038;OS=DN/20110300782RS=DN/20110300782" target="_blank">20110300782</a></td>
<td valign="top">APPARATUSES AND METHODS FOR CONDITIONING POLISHING PADS USED IN POLISHING MICRO-DEVICE WORKPIECES</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110300721.PGNR.&#038;OS=DN/20110300721RS=DN/20110300721" target="_blank">20110300721</a></td>
<td valign="top">Methods of Making Crystalline Tantalum Pentoxide</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110300689.PGNR.&#038;OS=DN/20110300689RS=DN/20110300689" target="_blank">20110300689</a></td>
<td valign="top">Methods of Forming Trench Isolation in the Fabrication of Integrated Circuitry and Methods of Fabricating Integrated Circuitry</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110299329.PGNR.&#038;OS=DN/20110299329RS=DN/20110299329" target="_blank">20110299329</a></td>
<td valign="top">BOTTOM ELECTRODE GEOMETRY FOR PHASE CHANGE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110298512.PGNR.&#038;OS=DN/20110298512RS=DN/20110298512" target="_blank">20110298512</a></td>
<td valign="top">CIRCUIT, SYSTEM AND METHOD FOR CONTROLLING READ LATENCY</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110298504.PGNR.&#038;OS=DN/20110298504RS=DN/20110298504" target="_blank">20110298504</a></td>
<td valign="top">CLOCK GENERATOR AND METHODS USING CLOSED LOOP DUTY CYCLE CORRECTION</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110298494.PGNR.&#038;OS=DN/20110298494RS=DN/20110298494" target="_blank">20110298494</a></td>
<td valign="top">METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110298014.PGNR.&#038;OS=DN/20110298014RS=DN/20110298014" target="_blank">20110298014</a></td>
<td valign="top">Cross-Point Memory Structures</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110298007.PGNR.&#038;OS=DN/20110298007RS=DN/20110298007" target="_blank">20110298007</a></td>
<td valign="top">SELECT DEVICES INCLUDING AN OPEN VOLUME, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS FOR FORMING SAME</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110297927.PGNR.&#038;OS=DN/20110297927RS=DN/20110297927" target="_blank">20110297927</a></td>
<td valign="top">OXIDE BASED MEMORY</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 06 December 2011</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-06-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-06-december-2011/#comments</comments>
		<pubDate>Wed, 07 Dec 2011 00:09:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15704</guid>
		<description><![CDATA[25 US patents granted on 06 December 2011 and assigned to Micron 1 8,074,159 Method and apparatus for detecting communication errors on a bus 2 8,074,122 Program failure recovery 3 8,073,986 Memory devices configured to identify an operating mode 4 8,073,890 Continuous high-frequency event filter 5 8,072,838 Control voltage tracking circuits, methods for recording a [...]]]></description>
			<content:encoded><![CDATA[<p>25 US patents granted on 06 December 2011 and assigned to Micron<br />
<span id="more-15704"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,074,159" target="_blank" rel="nofollow">8,074,159</a></td>
<td valign="top">Method and apparatus for detecting communication errors on a bus</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,074,122" target="_blank" rel="nofollow">8,074,122</a></td>
<td valign="top">Program failure recovery</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,073,986" target="_blank" rel="nofollow">8,073,986</a></td>
<td valign="top">Memory devices configured to identify an operating mode</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,073,890" target="_blank" rel="nofollow">8,073,890</a></td>
<td valign="top">Continuous high-frequency event filter</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,838" target="_blank" rel="nofollow">8,072,838</a></td>
<td valign="top">Control voltage tracking circuits, methods for recording a control voltage for a clock synchronization circuit and methods for setting a voltage controlled delay</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,836" target="_blank" rel="nofollow">8,072,836</a></td>
<td valign="top">Systems, methods and devices for arbitrating die stack position in a multi-die stack device</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,820" target="_blank" rel="nofollow">8,072,820</a></td>
<td valign="top">System and method for reducing pin-count of memory devices, and memory device testers for same</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,816" target="_blank" rel="nofollow">8,072,816</a></td>
<td valign="top">Memory block reallocation in a flash memory device</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,814" target="_blank" rel="nofollow">8,072,814</a></td>
<td valign="top">NAND with back biased operation</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,812" target="_blank" rel="nofollow">8,072,812</a></td>
<td valign="top">Sensing of memory cells in NAND flash</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,523" target="_blank" rel="nofollow">8,072,523</a></td>
<td valign="top">Redundancy in column parallel or row architectures</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,520" target="_blank" rel="nofollow">8,072,520</a></td>
<td valign="top">Dual pinned diode pixel with shutter</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,504" target="_blank" rel="nofollow">8,072,504</a></td>
<td valign="top">Method and system for aiding user alignment for capturing partially overlapping digital images</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,249" target="_blank" rel="nofollow">8,072,249</a></td>
<td valign="top">Clock jitter compensated clock circuits and methods for generating jitter compensated clock signals</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,082" target="_blank" rel="nofollow">8,072,082</a></td>
<td valign="top">Pre-encapsulated cavity interposer</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,055" target="_blank" rel="nofollow">8,072,055</a></td>
<td valign="top">High density stacked die assemblies, structures incorporated therein and methods of fabricating the assemblies</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,054" target="_blank" rel="nofollow">8,072,054</a></td>
<td valign="top">Lead frame</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,072,037" target="_blank" rel="nofollow">8,072,037</a></td>
<td valign="top">Method and system for electrically coupling a chip to chip package</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,480" target="_blank" rel="nofollow">8,071,480</a></td>
<td valign="top">Method and apparatuses for removing polysilicon from semiconductor workpieces</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,476" target="_blank" rel="nofollow">8,071,476</a></td>
<td valign="top">Cobalt titanium oxide dielectric films</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,467" target="_blank" rel="nofollow">8,071,467</a></td>
<td valign="top">Methods of forming patterns, and methods of forming integrated circuits</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,443" target="_blank" rel="nofollow">8,071,443</a></td>
<td valign="top">Method of forming lutetium and lanthanum dielectric structures</td>
</tr>
<tr>
<td valign="top" align="right">23</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,441" target="_blank" rel="nofollow">8,071,441</a></td>
<td valign="top">Methods of forming DRAM arrays</td>
</tr>
<tr>
<td valign="top" align="right">24</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,416" target="_blank" rel="nofollow">8,071,416</a></td>
<td valign="top">Method of forming a uniform color filter array</td>
</tr>
<tr>
<td valign="top" align="right">25</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,071,262" target="_blank" rel="nofollow">8,071,262</a></td>
<td valign="top">Reticles with subdivided blocking regions</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patent applications published on 01 December 2011</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-01-december-2011/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-01-december-2011/#comments</comments>
		<pubDate>Thu, 01 Dec 2011 23:20:33 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15664</guid>
		<description><![CDATA[11 US patent applications published on 01 December 2011 and assigned to Micron 1 20110296227 MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM 2 20110296144 REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION 3 20110296093 PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE 4 [...]]]></description>
			<content:encoded><![CDATA[<p>11 US patent applications published on 01 December 2011 and assigned to Micron<br />
<span id="more-15664"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110296227.PGNR.&#038;OS=DN/20110296227RS=DN/20110296227" target="_blank">20110296227</a></td>
<td valign="top">MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110296144.PGNR.&#038;OS=DN/20110296144RS=DN/20110296144" target="_blank">20110296144</a></td>
<td valign="top">REDUCING DATA HAZARDS IN PIPELINED PROCESSORS TO PROVIDE HIGH PROCESSOR UTILIZATION</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110296093.PGNR.&#038;OS=DN/20110296093RS=DN/20110296093" target="_blank">20110296093</a></td>
<td valign="top">PROGRAM AND SENSE OPERATIONS IN A NON-VOLATILE MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110296077.PGNR.&#038;OS=DN/20110296077RS=DN/20110296077" target="_blank">20110296077</a></td>
<td valign="top">MEMORY HUB ARCHITECTURE HAVING PROGRAMMABLE LANE WIDTHS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110294294.PGNR.&#038;OS=DN/20110294294RS=DN/20110294294" target="_blank">20110294294</a></td>
<td valign="top">PROTECTIVE COATING FOR PLANARIZATION</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110293833.PGNR.&#038;OS=DN/20110293833RS=DN/20110293833" target="_blank">20110293833</a></td>
<td valign="top">Zwitterionic Block Copolymers and Methods</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110291237.PGNR.&#038;OS=DN/20110291237RS=DN/20110291237" target="_blank">20110291237</a></td>
<td valign="top">LANTHANIDE DIELECTRIC WITH CONTROLLED INTERFACES</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110291224.PGNR.&#038;OS=DN/20110291224RS=DN/20110291224" target="_blank">20110291224</a></td>
<td valign="top">EFFICIENT PITCH MULTIPLICATION PROCESS</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110291146.PGNR.&#038;OS=DN/20110291146RS=DN/20110291146" target="_blank">20110291146</a></td>
<td valign="top">DRY FLUX BONDING DEVICE AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110291065.PGNR.&#038;OS=DN/20110291065RS=DN/20110291065" target="_blank">20110291065</a></td>
<td valign="top">PHASE CHANGE MEMORY CELL STRUCTURES AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20110291064.PGNR.&#038;OS=DN/20110291064RS=DN/20110291064" target="_blank">20110291064</a></td>
<td valign="top">RESISTANCE VARIABLE MEMORY CELL STRUCTURES AND METHODS</td>
</tr>
</table>
]]></content:encoded>
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		<title>Micron patents granted on 29 November 2011</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-29-november-2011/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-29-november-2011/#comments</comments>
		<pubDate>Tue, 29 Nov 2011 15:45:25 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=15622</guid>
		<description><![CDATA[15 US patents granted on 29 November 2011 and assigned to Micron 1 8,069,382 Memory cell programming 2 8,069,377 Integrated circuit having memory array including ECC and column redundancy and method of operating the same 3 8,069,300 Solid state storage device controller with expansion mode 4 8,068,380 Block repair scheme 5 8,068,374 Current mode memory [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patents granted on 29 November 2011 and assigned to Micron<br />
<span id="more-15622"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,069,382" target="_blank" rel="nofollow">8,069,382</a></td>
<td valign="top">Memory cell programming</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,069,377" target="_blank" rel="nofollow">8,069,377</a></td>
<td valign="top">Integrated circuit having memory array including ECC and column redundancy and method of operating the same</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,069,300" target="_blank" rel="nofollow">8,069,300</a></td>
<td valign="top">Solid state storage device controller with expansion mode</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,068,380" target="_blank" rel="nofollow">8,068,380</a></td>
<td valign="top">Block repair scheme</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,068,374" target="_blank" rel="nofollow">8,068,374</a></td>
<td valign="top">Current mode memory apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,068,367" target="_blank" rel="nofollow">8,068,367</a></td>
<td valign="top">Reference current sources</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,068,366" target="_blank" rel="nofollow">8,068,366</a></td>
<td valign="top">Analog read and write paths in a solid state memory device</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,068,046" target="_blank" rel="nofollow">8,068,046</a></td>
<td valign="top">Methods of quantizing signals using variable reference signals</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,827" target="_blank" rel="nofollow">8,067,827</a></td>
<td valign="top">Stacked microelectronic device assemblies</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,803" target="_blank" rel="nofollow">8,067,803</a></td>
<td valign="top">Memory devices, transistor devices and related methods</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,794" target="_blank" rel="nofollow">8,067,794</a></td>
<td valign="top">Conductive layers for hafnium silicon oxynitride films</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,286" target="_blank" rel="nofollow">8,067,286</a></td>
<td valign="top">Methods of forming recessed access devices associated with semiconductor constructions</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,260" target="_blank" rel="nofollow">8,067,260</a></td>
<td valign="top">Fabricating sub-lithographic contacts</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,067,133" target="_blank" rel="nofollow">8,067,133</a></td>
<td valign="top">Phase shift mask with two-phase clear feature</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=8,065,792" target="_blank" rel="nofollow">8,065,792</a></td>
<td valign="top">Method for packaging circuits</td>
</tr>
</table>
]]></content:encoded>
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