<?xml version="1.0" encoding="UTF-8"?>
<rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:wfw="http://wellformedweb.org/CommentAPI/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	xmlns:sy="http://purl.org/rss/1.0/modules/syndication/"
	xmlns:slash="http://purl.org/rss/1.0/modules/slash/"
	>

<channel>
	<title>Latest Patents &#187; Micron</title>
	<atom:link href="http://www.latestpatents.com/category/micron/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.latestpatents.com</link>
	<description>Latest Patents of Leading Technology Companies</description>
	<lastBuildDate>Thu, 11 Mar 2010 15:41:21 +0000</lastBuildDate>
	<generator>http://wordpress.org/?v=2.8.4</generator>
	<language>en</language>
	<sy:updatePeriod>hourly</sy:updatePeriod>
	<sy:updateFrequency>1</sy:updateFrequency>
			<item>
		<title>Micron patent applications published on 11 March 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-11-march-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-11-march-2010/#comments</comments>
		<pubDate>Thu, 11 Mar 2010 15:30:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8328</guid>
		<description><![CDATA[15 US patent applications published on 11 March 2010 and assigned to Micron



1
20100064352
MIXED ENCLAVE OPERATION IN A COMPUTER NETWORK


2
20100064186
METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY


3
20100064114
STACKED DEVICE IDENTIFICATION ASSIGNMENT


4
20100064089
BUS WIDTH NEGOTIATION


5
20100062580
Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer


6
20100062579
SELF-ALIGNED TRENCH FORMATION


7
20100062571
MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES


8
20100061165
Circuitry and Methods [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patent applications published on 11 March 2010 and assigned to Micron<br />
<span id="more-8328"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100064352.PGNR.&#038;OS=DN/20100064352RS=DN/20100064352" target="_blank">20100064352</a></td>
<td valign="top">MIXED ENCLAVE OPERATION IN A COMPUTER NETWORK</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100064186.PGNR.&#038;OS=DN/20100064186RS=DN/20100064186" target="_blank">20100064186</a></td>
<td valign="top">METHODS, APPARATUS, AND SYSTEMS TO REPAIR MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100064114.PGNR.&#038;OS=DN/20100064114RS=DN/20100064114" target="_blank">20100064114</a></td>
<td valign="top">STACKED DEVICE IDENTIFICATION ASSIGNMENT</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100064089.PGNR.&#038;OS=DN/20100064089RS=DN/20100064089" target="_blank">20100064089</a></td>
<td valign="top">BUS WIDTH NEGOTIATION</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100062580.PGNR.&#038;OS=DN/20100062580RS=DN/20100062580" target="_blank">20100062580</a></td>
<td valign="top">Fabrication processes for forming dual depth trenches using a dry etch that deposits a polymer</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100062579.PGNR.&#038;OS=DN/20100062579RS=DN/20100062579" target="_blank">20100062579</a></td>
<td valign="top">SELF-ALIGNED TRENCH FORMATION</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100062571.PGNR.&#038;OS=DN/20100062571RS=DN/20100062571" target="_blank">20100062571</a></td>
<td valign="top">MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING MICROELECTRONIC DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100061165.PGNR.&#038;OS=DN/20100061165RS=DN/20100061165" target="_blank">20100061165</a></td>
<td valign="top">Circuitry and Methods for Improving Differential Signals That Cross Power Domains</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100061155.PGNR.&#038;OS=DN/20100061155RS=DN/20100061155" target="_blank">20100061155</a></td>
<td valign="top">MEMORY ARRAY SEGMENTATION AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100061147.PGNR.&#038;OS=DN/20100061147RS=DN/20100061147" target="_blank">20100061147</a></td>
<td valign="top">REDUCING EFFECTS OF PROGRAM DISTURB IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100060335.PGNR.&#038;OS=DN/20100060335RS=DN/20100060335" target="_blank">20100060335</a></td>
<td valign="top">Seamless Coarse and Fine Delay Structure for High Performance DLL</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100060320.PGNR.&#038;OS=DN/20100060320RS=DN/20100060320" target="_blank">20100060320</a></td>
<td valign="top">SIGNAL DRIVER CIRCUIT HAVING AN ADJUSTABLE OUTPUT VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100059898.PGNR.&#038;OS=DN/20100059898RS=DN/20100059898" target="_blank">20100059898</a></td>
<td valign="top">SIGNAL DELIVERY IN STACKED DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100059897.PGNR.&#038;OS=DN/20100059897RS=DN/20100059897" target="_blank">20100059897</a></td>
<td valign="top">INTERCONNECT STRUCTURES FOR STACKED DIES, INCLUDING PENETRATING STRUCTURES FOR THROUGH-SILICON VIAS, AND ASSOCIATED SYSTEMS AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100059705.PGNR.&#038;OS=DN/20100059705RS=DN/20100059705" target="_blank">20100059705</a></td>
<td valign="top">METHOD AND APPARATUS FOR REMOVING MATERIAL FROM MICROFEATURE WORKPIECES</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-11-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 09 March 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-09-march-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-09-march-2010/#comments</comments>
		<pubDate>Tue, 09 Mar 2010 17:30:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8289</guid>
		<description><![CDATA[16 US patents granted on 09 March 2010 and assigned to Micron



1
7,676,710
Error detection, documentation, and correction in a flash memory device


2
7,676,648
Method for manipulating data in a group of processing elements to perform a reflection of the data


3
7,676,627
Single segment data object management


4
7,675,778
Memory devices having reduced word line current and method of operating and manufacturing the same


5
7,675,772
Multilevel [...]]]></description>
			<content:encoded><![CDATA[<p>16 US patents granted on 09 March 2010 and assigned to Micron<br />
<span id="more-8289"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,710" target="_blank" rel="nofollow">7,676,710</a></td>
<td valign="top">Error detection, documentation, and correction in a flash memory device</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,648" target="_blank" rel="nofollow">7,676,648</a></td>
<td valign="top">Method for manipulating data in a group of processing elements to perform a reflection of the data</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,676,627" target="_blank" rel="nofollow">7,676,627</a></td>
<td valign="top">Single segment data object management</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,778" target="_blank" rel="nofollow">7,675,778</a></td>
<td valign="top">Memory devices having reduced word line current and method of operating and manufacturing the same</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,772" target="_blank" rel="nofollow">7,675,772</a></td>
<td valign="top">Multilevel memory cell operation</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,526" target="_blank" rel="nofollow">7,675,526</a></td>
<td valign="top">System and method for multi-sampling primitives to reduce aliasing</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,324" target="_blank" rel="nofollow">7,675,324</a></td>
<td valign="top">Pre-driver logic</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,169" target="_blank" rel="nofollow">7,675,169</a></td>
<td valign="top">Apparatus and method for packaging circuits</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,131" target="_blank" rel="nofollow">7,675,131</a></td>
<td valign="top">Flip-chip image sensor packages and methods of fabricating the same</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,675,093" target="_blank" rel="nofollow">7,675,093</a></td>
<td valign="top">Antiblooming imaging apparatus, system, and methods</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,698" target="_blank" rel="nofollow">7,674,698</a></td>
<td valign="top">Metal-substituted transistor gates</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,683" target="_blank" rel="nofollow">7,674,683</a></td>
<td valign="top">Bulk-isolated PN diode and method of forming a bulk-isolated PN diode</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,670" target="_blank" rel="nofollow">7,674,670</a></td>
<td valign="top">Methods of forming threshold voltage implant regions</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,669" target="_blank" rel="nofollow">7,674,669</a></td>
<td valign="top">FIN field effect transistor</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,655" target="_blank" rel="nofollow">7,674,655</a></td>
<td valign="top">Semiconductor assemblies and methods of manufacturing such assemblies including forming trenches in a first side of the molding material</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,674,652" target="_blank" rel="nofollow">7,674,652</a></td>
<td valign="top">Methods of forming an integrated circuit package</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-09-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 04 March 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-04-march-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-04-march-2010/#comments</comments>
		<pubDate>Thu, 04 Mar 2010 17:11:40 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8250</guid>
		<description><![CDATA[17 US patent applications published on 04 March 2010 and assigned to Micron



1
20100058124
SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME


2
20100057802
METHOD AND SYSTEM FOR UPDATING A SEARCH ENGINE


3
20100055871
MEMORY IN LOGIC CELL


4
20100055837
MULTI-CHIP MODULE AND METHODS


5
20100054070
METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES


6
20100054068
TEMPERATURE COMPENSATION OF MEMORY [...]]]></description>
			<content:encoded><![CDATA[<p>17 US patent applications published on 04 March 2010 and assigned to Micron<br />
<span id="more-8250"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100058124.PGNR.&#038;OS=DN/20100058124RS=DN/20100058124" target="_blank">20100058124</a></td>
<td valign="top">SYSTEM AND METHOD FOR INITIALIZING A MEMORY SYSTEM, AND MEMORY DEVICE AND PROCESSOR-BASED SYSTEM USING SAME</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100057802.PGNR.&#038;OS=DN/20100057802RS=DN/20100057802" target="_blank">20100057802</a></td>
<td valign="top">METHOD AND SYSTEM FOR UPDATING A SEARCH ENGINE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100055871.PGNR.&#038;OS=DN/20100055871RS=DN/20100055871" target="_blank">20100055871</a></td>
<td valign="top">MEMORY IN LOGIC CELL</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100055837.PGNR.&#038;OS=DN/20100055837RS=DN/20100055837" target="_blank">20100055837</a></td>
<td valign="top">MULTI-CHIP MODULE AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100054070.PGNR.&#038;OS=DN/20100054070RS=DN/20100054070" target="_blank">20100054070</a></td>
<td valign="top">METHOD AND SYSTEM FOR CONTROLLING REFRESH TO AVOID MEMORY CELL DATA LOSSES</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100054068.PGNR.&#038;OS=DN/20100054068RS=DN/20100054068" target="_blank">20100054068</a></td>
<td valign="top">TEMPERATURE COMPENSATION OF MEMORY SIGNALS USING DIGITAL SIGNALS</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100054058.PGNR.&#038;OS=DN/20100054058RS=DN/20100054058" target="_blank">20100054058</a></td>
<td valign="top">SYSTEMS AND METHODS FOR ISSUING ADDRESS AND DATA SIGNALS TO A MEMORY ARRAY</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100054041.PGNR.&#038;OS=DN/20100054041RS=DN/20100054041" target="_blank">20100054041</a></td>
<td valign="top">ADJUSTING PROGRAMMING OR ERASE VOLTAGE PULSES IN RESPONSE TO A RATE OF PROGRAMMING OR ERASING</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100053353.PGNR.&#038;OS=DN/20100053353RS=DN/20100053353" target="_blank">20100053353</a></td>
<td valign="top">Method and system for aiding user alignment for capturing partially overlapping digital images</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100053157.PGNR.&#038;OS=DN/20100053157RS=DN/20100053157" target="_blank">20100053157</a></td>
<td valign="top">METHODS AND APPARATUS FOR RENDERING OR PREPARING DIGITAL OBJECTS OR PORTIONS THEREOF FOR SUBSEQUENT PROCESSING</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100052777.PGNR.&#038;OS=DN/20100052777RS=DN/20100052777" target="_blank">20100052777</a></td>
<td valign="top">High Performance Input Receiver Circuit For Reduced-Swing Inputs</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100052183.PGNR.&#038;OS=DN/20100052183RS=DN/20100052183" target="_blank">20100052183</a></td>
<td valign="top">MICROFEATURE WORKPIECE SUBSTRATES HAVING THROUGH-SUBSTRATE VIAS, AND ASSOCIATED METHODS OF FORMATION</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100052157.PGNR.&#038;OS=DN/20100052157RS=DN/20100052157" target="_blank">20100052157</a></td>
<td valign="top">CHANNEL FOR A SEMICONDUCTOR DIE AND METHODS OF FORMATION</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100052086.PGNR.&#038;OS=DN/20100052086RS=DN/20100052086" target="_blank">20100052086</a></td>
<td valign="top">ELECTRONIC DEVICE PACKAGES AND METHODS OF FABRICATING ELECTRONIC DEVICE PACKAGES</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100052027.PGNR.&#038;OS=DN/20100052027RS=DN/20100052027" target="_blank">20100052027</a></td>
<td valign="top">DRAM Layout with Vertical FETS and Method of Formation</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100051895.PGNR.&#038;OS=DN/20100051895RS=DN/20100051895" target="_blank">20100051895</a></td>
<td valign="top">PHASE CHANGE MATERIAL, A PHASE CHANGE RANDOM ACCESS MEMORY DEVICE INCLUDING THE PHASE CHANGE MATERIAL, A SEMICONDUCTOR STRUCTURE INCLUDING THE PHASE CHANGE MATERIAL, AND METHODS OF FORMING THE PHASE CHANGE MATERIAL</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100051577.PGNR.&#038;OS=DN/20100051577RS=DN/20100051577" target="_blank">20100051577</a></td>
<td valign="top">COPPER LAYER PROCESSING</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-04-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 02 March 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-02-march-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-02-march-2010/#comments</comments>
		<pubDate>Tue, 02 Mar 2010 18:04:26 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8212</guid>
		<description><![CDATA[15 US patents granted on 02 March 2010 and assigned to Micron



1
7,673,094
Memory devices with buffered command address bus


2
7,672,171
Non-planar flash memory array with shielded floating gates on silicon mesas


3
7,671,914
Increasing readout speed in CMOS APS sensors through block readout


4
7,671,648
System and method for an accuracy-enhanced DLL during a measure initialization mode


5
7,671,647
Apparatus and method for trimming static delay of [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patents granted on 02 March 2010 and assigned to Micron<br />
<span id="more-8212"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,673,094" target="_blank" rel="nofollow">7,673,094</a></td>
<td valign="top">Memory devices with buffered command address bus</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,672,171" target="_blank" rel="nofollow">7,672,171</a></td>
<td valign="top">Non-planar flash memory array with shielded floating gates on silicon mesas</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,914" target="_blank" rel="nofollow">7,671,914</a></td>
<td valign="top">Increasing readout speed in CMOS APS sensors through block readout</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,648" target="_blank" rel="nofollow">7,671,648</a></td>
<td valign="top">System and method for an accuracy-enhanced DLL during a measure initialization mode</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,647" target="_blank" rel="nofollow">7,671,647</a></td>
<td valign="top">Apparatus and method for trimming static delay of a synchronizing circuit</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,644" target="_blank" rel="nofollow">7,671,644</a></td>
<td valign="top">Process insensitive delay line</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,459" target="_blank" rel="nofollow">7,671,459</a></td>
<td valign="top">Microelectronic devices, stacked microelectronic devices, and methods for manufacturing such devices</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,671,407" target="_blank" rel="nofollow">7,671,407</a></td>
<td valign="top">Embedded trap direct tunnel non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,958" target="_blank" rel="nofollow">7,670,958</a></td>
<td valign="top">Etching methods</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,907" target="_blank" rel="nofollow">7,670,907</a></td>
<td valign="top">Isolation regions for semiconductor devices and their formation</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,905" target="_blank" rel="nofollow">7,670,905</a></td>
<td valign="top">Semiconductor processing methods, and methods of forming flash memory structures</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,898" target="_blank" rel="nofollow">7,670,898</a></td>
<td valign="top">Methods of forming semiconductor constructions</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,646" target="_blank" rel="nofollow">7,670,646</a></td>
<td valign="top">Methods for atomic-layer deposition</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,469" target="_blank" rel="nofollow">7,670,469</a></td>
<td valign="top">Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,670,466" target="_blank" rel="nofollow">7,670,466</a></td>
<td valign="top">Methods and apparatuses for electrochemical-mechanical polishing</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-02-march-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 25 February 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-25-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-25-february-2010/#comments</comments>
		<pubDate>Thu, 25 Feb 2010 14:27:28 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8171</guid>
		<description><![CDATA[14 US patent applications published on 25 February 2010 and assigned to Micron



1
20100047966
INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS


2
20100047945
Methods Of Forming Particle-Containing Materials


3
20100046311
ON-CHIP TEMPERATURE SENSOR


4
20100046305
ERASE OPERATION IN A FLASH DRIVE MEMORY


5
20100046303
PROGRAM-VERIFY METHOD


6
20100046300
REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE


7
20100046299
PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY


8
20100046295
FAST DATA ACCESS MODE IN A MEMORY [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patent applications published on 25 February 2010 and assigned to Micron<br />
<span id="more-8171"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100047966.PGNR.&#038;OS=DN/20100047966RS=DN/20100047966" target="_blank">20100047966</a></td>
<td valign="top">INTEGRATED CIRCUIT APPARATUS, SYSTEMS, AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100047945.PGNR.&#038;OS=DN/20100047945RS=DN/20100047945" target="_blank">20100047945</a></td>
<td valign="top">Methods Of Forming Particle-Containing Materials</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046311.PGNR.&#038;OS=DN/20100046311RS=DN/20100046311" target="_blank">20100046311</a></td>
<td valign="top">ON-CHIP TEMPERATURE SENSOR</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046305.PGNR.&#038;OS=DN/20100046305RS=DN/20100046305" target="_blank">20100046305</a></td>
<td valign="top">ERASE OPERATION IN A FLASH DRIVE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046303.PGNR.&#038;OS=DN/20100046303RS=DN/20100046303" target="_blank">20100046303</a></td>
<td valign="top">PROGRAM-VERIFY METHOD</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046300.PGNR.&#038;OS=DN/20100046300RS=DN/20100046300" target="_blank">20100046300</a></td>
<td valign="top">REDUCTION OF QUICK CHARGE LOSS EFFECT IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046299.PGNR.&#038;OS=DN/20100046299RS=DN/20100046299" target="_blank">20100046299</a></td>
<td valign="top">PROGRAMMING RATE IDENTIFICATION AND CONTROL IN A SOLID STATE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100046295.PGNR.&#038;OS=DN/20100046295RS=DN/20100046295" target="_blank">20100046295</a></td>
<td valign="top">FAST DATA ACCESS MODE IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100045354.PGNR.&#038;OS=DN/20100045354RS=DN/20100045354" target="_blank">20100045354</a></td>
<td valign="top">DELAY-LOCK LOOP AND METHOD ADAPTING ITSELF TO OPERATE OVER A WIDE FREQUENCY RANGE</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100045341.PGNR.&#038;OS=DN/20100045341RS=DN/20100045341" target="_blank">20100045341</a></td>
<td valign="top">Method and Apparatus for High Resolution ZQ Calibration</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100044876.PGNR.&#038;OS=DN/20100044876RS=DN/20100044876" target="_blank">20100044876</a></td>
<td valign="top">CONDUCTIVE STRUCTURES FOR MICROFEATURE DEVICES AND METHODS FOR FABRICATING MICROFEATURE DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100044763.PGNR.&#038;OS=DN/20100044763RS=DN/20100044763" target="_blank">20100044763</a></td>
<td valign="top">Method and apparatus providing an imager with a shared power supply and readout line for pixels</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100044664.PGNR.&#038;OS=DN/20100044664RS=DN/20100044664" target="_blank">20100044664</a></td>
<td valign="top">MEMORY DEVICES AND METHODS OF FORMING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100043824.PGNR.&#038;OS=DN/20100043824RS=DN/20100043824" target="_blank">20100043824</a></td>
<td valign="top">MICROELECTRONIC SUBSTRATE CLEANING SYSTEMS WITH POLYELECTROLYTE AND ASSOCIATED METHODS</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-25-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 23 February 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-23-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-23-february-2010/#comments</comments>
		<pubDate>Tue, 23 Feb 2010 13:40:26 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8133</guid>
		<description><![CDATA[15 US patents granted on 23 February 2010 and assigned to Micron



1
7,669,092
Apparatus, method, and system of NAND defect management


2
7,669,064
Diagnostic and managing distributed processor system


3
7,669,027
Memory command delay balancing in a daisy-chained memory topology


4
7,668,893
Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders


5
7,668,012
Memory cell programming


6
7,668,000
Method and apparatus providing a cross-point memory [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patents granted on 23 February 2010 and assigned to Micron<br />
<span id="more-8133"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,092" target="_blank" rel="nofollow">7,669,092</a></td>
<td valign="top">Apparatus, method, and system of NAND defect management</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,064" target="_blank" rel="nofollow">7,669,064</a></td>
<td valign="top">Diagnostic and managing distributed processor system</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,669,027" target="_blank" rel="nofollow">7,669,027</a></td>
<td valign="top">Memory command delay balancing in a daisy-chained memory topology</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,893" target="_blank" rel="nofollow">7,668,893</a></td>
<td valign="top">Data generator having linear feedback shift registers for generating data pattern in forward and reverse orders</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,012" target="_blank" rel="nofollow">7,668,012</a></td>
<td valign="top">Memory cell programming</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,668,000" target="_blank" rel="nofollow">7,668,000</a></td>
<td valign="top">Method and apparatus providing a cross-point memory array using a variable resistance memory cell and capacitance</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,632" target="_blank" rel="nofollow">7,667,632</a></td>
<td valign="top">Quantizing circuits for semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,260" target="_blank" rel="nofollow">7,667,260</a></td>
<td valign="top">Nanoscale floating gate and methods of formation</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,258" target="_blank" rel="nofollow">7,667,258</a></td>
<td valign="top">Double-sided container capacitors using a sacrificial layer</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,667,234" target="_blank" rel="nofollow">7,667,234</a></td>
<td valign="top">High density memory array having increased channel widths</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,801" target="_blank" rel="nofollow">7,666,801</a></td>
<td valign="top">Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,797" target="_blank" rel="nofollow">7,666,797</a></td>
<td valign="top">Methods for forming semiconductor constructions, and methods for selectively etching silicon nitride relative to conductive material</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,788" target="_blank" rel="nofollow">7,666,788</a></td>
<td valign="top">Methods for forming conductive vias in semiconductor device components</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,776" target="_blank" rel="nofollow">7,666,776</a></td>
<td valign="top">Methods of forming conductive structures</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,666,578" target="_blank" rel="nofollow">7,666,578</a></td>
<td valign="top">Efficient pitch multiplication process</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-23-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 18 February 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-18-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-18-february-2010/#comments</comments>
		<pubDate>Thu, 18 Feb 2010 13:33:04 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8096</guid>
		<description><![CDATA[18 US patent applications published on 18 February 2010 and assigned to Micron



1
20100042908
DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD


2
20100042889
MEMORY SYSTEM AND METHOD USING A MEMORY DEVICE DIE STACKED WITH A LOGIC DIE USING DATA ENCODING, AND SYSTEM USING THE MEMORY SYSTEM


3
20100042750
CHAINED BUS METHOD AND DEVICE


4
20100041244
HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC


5
20100041180
Methods of Forming Semiconductor Constructions and [...]]]></description>
			<content:encoded><![CDATA[<p>18 US patent applications published on 18 February 2010 and assigned to Micron<br />
<span id="more-8096"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100042908.PGNR.&#038;OS=DN/20100042908RS=DN/20100042908" target="_blank">20100042908</a></td>
<td valign="top">DATA AND ERROR CORRECTION CODE MIXING DEVICE AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100042889.PGNR.&#038;OS=DN/20100042889RS=DN/20100042889" target="_blank">20100042889</a></td>
<td valign="top">MEMORY SYSTEM AND METHOD USING A MEMORY DEVICE DIE STACKED WITH A LOGIC DIE USING DATA ENCODING, AND SYSTEM USING THE MEMORY SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100042750.PGNR.&#038;OS=DN/20100042750RS=DN/20100042750" target="_blank">20100042750</a></td>
<td valign="top">CHAINED BUS METHOD AND DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100041244.PGNR.&#038;OS=DN/20100041244RS=DN/20100041244" target="_blank">20100041244</a></td>
<td valign="top">HAFNIUM TANTALUM OXYNITRIDE DIELECTRIC</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100041180.PGNR.&#038;OS=DN/20100041180RS=DN/20100041180" target="_blank">20100041180</a></td>
<td valign="top">Methods of Forming Semiconductor Constructions and Assemblies</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100040962.PGNR.&#038;OS=DN/20100040962RS=DN/20100040962" target="_blank">20100040962</a></td>
<td valign="top">MULTI-LAYER, ATTENUATED PHASE-SHIFTING MASK</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039877.PGNR.&#038;OS=DN/20100039877RS=DN/20100039877" target="_blank">20100039877</a></td>
<td valign="top">EXTERNAL CLOCK TRACKING PIPELINED LATCH SCHEME</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039869.PGNR.&#038;OS=DN/20100039869RS=DN/20100039869" target="_blank">20100039869</a></td>
<td valign="top">MULTI-STATE MEMORY CELL WITH ASYMMETRIC CHARGE TRAPPING</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039866.PGNR.&#038;OS=DN/20100039866RS=DN/20100039866" target="_blank">20100039866</a></td>
<td valign="top">SENSING OF MEMORY CELLS IN A SOLID STATE MEMORY DEVICE BY FIXED DISCHARGE OF A BIT LINE</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039864.PGNR.&#038;OS=DN/20100039864RS=DN/20100039864" target="_blank">20100039864</a></td>
<td valign="top">METHODS OF ERASE VERIFICATION FOR A FLASH MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039862.PGNR.&#038;OS=DN/20100039862RS=DN/20100039862" target="_blank">20100039862</a></td>
<td valign="top">READ OPERATION FOR NAND MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039860.PGNR.&#038;OS=DN/20100039860RS=DN/20100039860" target="_blank">20100039860</a></td>
<td valign="top">MEMORY DEVICES AND METHODS OF STORING DATA ON A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039147.PGNR.&#038;OS=DN/20100039147RS=DN/20100039147" target="_blank">20100039147</a></td>
<td valign="top">SEMICONDUCTOR DEVICES WITH SIGNAL SYNCHRONIZATION CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100039097.PGNR.&#038;OS=DN/20100039097RS=DN/20100039097" target="_blank">20100039097</a></td>
<td valign="top">METHODS AND APPARATUS FOR VOLTAGE SENSING AND REPORTING</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100038796.PGNR.&#038;OS=DN/20100038796RS=DN/20100038796" target="_blank">20100038796</a></td>
<td valign="top">HIGH ASPECT RATIO CONTACTS</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100038730.PGNR.&#038;OS=DN/20100038730RS=DN/20100038730" target="_blank">20100038730</a></td>
<td valign="top">SEMICONDUCTOR STRUCTURES INCLUDING A MOVABLE SWITCHING ELEMENT, SYSTEMS INCLUDING SAME AND METHODS OF FORMING SAME</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100038701.PGNR.&#038;OS=DN/20100038701RS=DN/20100038701" target="_blank">20100038701</a></td>
<td valign="top">INTEGRATED TWO DEVICE NON-VOLATILE MEMORY</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100038614.PGNR.&#038;OS=DN/20100038614RS=DN/20100038614" target="_blank">20100038614</a></td>
<td valign="top">METHODS OF FORMING A PHASE CHANGE MATERIAL, A PHASE CHANGE MATERIAL, A PHASE CHANGE RANDOM ACCESS MEMORY DEVICE INCLUDING THE PHASE CHANGE MATERIAL, AND A SEMICONDUCTOR STRUCTURE INCLUDING THE PHASE CHANGE MATERIAL</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-18-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 16 February 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-16-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-16-february-2010/#comments</comments>
		<pubDate>Tue, 16 Feb 2010 14:57:35 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8057</guid>
		<description><![CDATA[22 US patents granted on 16 February 2010 and assigned to Micron



1
7,664,999
Real time testing using on die termination (ODT) circuit


2
7,664,216
Digital frequency locked delay line


3
7,663,952
Capacitor supported precharging of memory digit lines


4
7,663,934
Program method with optimized voltage level for flash memory


5
7,663,930
Programming a non-volatile memory device


6
7,663,926
Cell deterioration warning apparatus and method


7
7,663,925
Method and apparatus for programming flash memory


8
7,663,901
Techniques for implementing [...]]]></description>
			<content:encoded><![CDATA[<p>22 US patents granted on 16 February 2010 and assigned to Micron<br />
<span id="more-8057"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,999" target="_blank" rel="nofollow">7,664,999</a></td>
<td valign="top">Real time testing using on die termination (ODT) circuit</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,664,216" target="_blank" rel="nofollow">7,664,216</a></td>
<td valign="top">Digital frequency locked delay line</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,952" target="_blank" rel="nofollow">7,663,952</a></td>
<td valign="top">Capacitor supported precharging of memory digit lines</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,934" target="_blank" rel="nofollow">7,663,934</a></td>
<td valign="top">Program method with optimized voltage level for flash memory</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,930" target="_blank" rel="nofollow">7,663,930</a></td>
<td valign="top">Programming a non-volatile memory device</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,926" target="_blank" rel="nofollow">7,663,926</a></td>
<td valign="top">Cell deterioration warning apparatus and method</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,925" target="_blank" rel="nofollow">7,663,925</a></td>
<td valign="top">Method and apparatus for programming flash memory</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,901" target="_blank" rel="nofollow">7,663,901</a></td>
<td valign="top">Techniques for implementing accurate device parameters stored in a database</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,232" target="_blank" rel="nofollow">7,663,232</a></td>
<td valign="top">Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,224" target="_blank" rel="nofollow">7,663,224</a></td>
<td valign="top">Semiconductor BGA package having a segmented voltage plane</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,206" target="_blank" rel="nofollow">7,663,206</a></td>
<td valign="top">Interposer including at least one passive element at least partially defined by a recess formed therein, system including same, and wafer-scale interposer</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,137" target="_blank" rel="nofollow">7,663,137</a></td>
<td valign="top">Phase change memory cell and method of formation</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,663,133" target="_blank" rel="nofollow">7,663,133</a></td>
<td valign="top">Memory elements having patterned electrodes and method of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,729" target="_blank" rel="nofollow">7,662,729</a></td>
<td valign="top">Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,719" target="_blank" rel="nofollow">7,662,719</a></td>
<td valign="top">Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,718" target="_blank" rel="nofollow">7,662,718</a></td>
<td valign="top">Trim process for critical dimension control for integrated circuits</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,701" target="_blank" rel="nofollow">7,662,701</a></td>
<td valign="top">Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,693" target="_blank" rel="nofollow">7,662,693</a></td>
<td valign="top">Lanthanide dielectric with controlled interfaces</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,658" target="_blank" rel="nofollow">7,662,658</a></td>
<td valign="top">Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,649" target="_blank" rel="nofollow">7,662,649</a></td>
<td valign="top">Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,648" target="_blank" rel="nofollow">7,662,648</a></td>
<td valign="top">Integrated circuit inspection system</td>
</tr>
<tr>
<td valign="top" align="right">22</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,662,299" target="_blank" rel="nofollow">7,662,299</a></td>
<td valign="top">Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-16-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 11 February 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-11-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-11-february-2010/#comments</comments>
		<pubDate>Thu, 11 Feb 2010 14:13:11 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=8018</guid>
		<description><![CDATA[10 US patent applications published on 11 February 2010 and assigned to Micron



1
20100036994
FLEXIBLE AND EXPANDABLE MEMORY ARCHITECTURES


2
20100036989
SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS


3
20100035404
Methods of Forming Trench Isolation and Methods of Forming Arrays of FLASH Memory Cells


4
20100035395
METHODS OF FORMING MEMORY CELLS ON PILLARS AND MEMORIES WITH MEMORY CELLS ON PILLARS


5
20100034480
Methods and apparatus for flat region [...]]]></description>
			<content:encoded><![CDATA[<p>10 US patent applications published on 11 February 2010 and assigned to Micron<br />
<span id="more-8018"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100036994.PGNR.&#038;OS=DN/20100036994RS=DN/20100036994" target="_blank">20100036994</a></td>
<td valign="top">FLEXIBLE AND EXPANDABLE MEMORY ARCHITECTURES</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100036989.PGNR.&#038;OS=DN/20100036989RS=DN/20100036989" target="_blank">20100036989</a></td>
<td valign="top">SYSTEM AND METHOD FOR MEMORY HUB-BASED EXPANSION BUS</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100035404.PGNR.&#038;OS=DN/20100035404RS=DN/20100035404" target="_blank">20100035404</a></td>
<td valign="top">Methods of Forming Trench Isolation and Methods of Forming Arrays of FLASH Memory Cells</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100035395.PGNR.&#038;OS=DN/20100035395RS=DN/20100035395" target="_blank">20100035395</a></td>
<td valign="top">METHODS OF FORMING MEMORY CELLS ON PILLARS AND MEMORIES WITH MEMORY CELLS ON PILLARS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100034480.PGNR.&#038;OS=DN/20100034480RS=DN/20100034480" target="_blank">20100034480</a></td>
<td valign="top">Methods and apparatus for flat region image filtering</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100034034.PGNR.&#038;OS=DN/20100034034RS=DN/20100034034" target="_blank">20100034034</a></td>
<td valign="top">METHODS, CIRCUITS, AND SYSTEMS TO SELECT MEMORY REGIONS</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100034016.PGNR.&#038;OS=DN/20100034016RS=DN/20100034016" target="_blank">20100034016</a></td>
<td valign="top">PHASE CHANGE MEMORY STRUCTURES AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100033232.PGNR.&#038;OS=DN/20100033232RS=DN/20100033232" target="_blank">20100033232</a></td>
<td valign="top">VARIABLE STAGE CHARGE PUMP AND METHOD FOR PROVIDING BOOSTED OUTPUT VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100032746.PGNR.&#038;OS=DN/20100032746RS=DN/20100032746" target="_blank">20100032746</a></td>
<td valign="top">USE OF DILUTE STEAM AMBIENT FOR IMPROVEMENT OF FLASH DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100032314.PGNR.&#038;OS=DN/20100032314RS=DN/20100032314" target="_blank">20100032314</a></td>
<td valign="top">METHODS AND APPARATUS FOR SELECTIVELY REMOVING CONDUCTIVE MATERIAL FROM A MICROELECTRONIC SUBSTRATE</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-11-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 09 February 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-09-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-09-february-2010/#comments</comments>
		<pubDate>Tue, 09 Feb 2010 14:33:52 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7979</guid>
		<description><![CDATA[16 US patents granted on 09 February 2010 and assigned to Micron



1
7,660,708
S-matrix technique for circuit simulation


2
7,660,187
Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM


3
7,660,172
Method and apparatus for synchronizing data from memory arrays


4
7,660,158
Programming method to reduce gate coupling interference for non-volatile memory


5
7,660,144
High-performance one-transistor memory cell


6
7,659,630
Interconnect structures with interlayer dielectric


7
7,659,612
Semiconductor components having encapsulated [...]]]></description>
			<content:encoded><![CDATA[<p>16 US patents granted on 09 February 2010 and assigned to Micron<br />
<span id="more-7979"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,708" target="_blank" rel="nofollow">7,660,708</a></td>
<td valign="top">S-matrix technique for circuit simulation</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,187" target="_blank" rel="nofollow">7,660,187</a></td>
<td valign="top">Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,172" target="_blank" rel="nofollow">7,660,172</a></td>
<td valign="top">Method and apparatus for synchronizing data from memory arrays</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,158" target="_blank" rel="nofollow">7,660,158</a></td>
<td valign="top">Programming method to reduce gate coupling interference for non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,660,144" target="_blank" rel="nofollow">7,660,144</a></td>
<td valign="top">High-performance one-transistor memory cell</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,630" target="_blank" rel="nofollow">7,659,630</a></td>
<td valign="top">Interconnect structures with interlayer dielectric</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,612" target="_blank" rel="nofollow">7,659,612</a></td>
<td valign="top">Semiconductor components having encapsulated through wire interconnects (TWI)</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,560" target="_blank" rel="nofollow">7,659,560</a></td>
<td valign="top">Transistor structures</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,211" target="_blank" rel="nofollow">7,659,211</a></td>
<td valign="top">Method and apparatus for fabricating a memory device with a dielectric etch stop layer</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,210" target="_blank" rel="nofollow">7,659,210</a></td>
<td valign="top">Nano-crystal etch process</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,208" target="_blank" rel="nofollow">7,659,208</a></td>
<td valign="top">Method for forming high density patterns</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,205" target="_blank" rel="nofollow">7,659,205</a></td>
<td valign="top">Amorphous carbon-based non-volatile memory</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,181" target="_blank" rel="nofollow">7,659,181</a></td>
<td valign="top">Sub-micron space liner and filler process</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,161" target="_blank" rel="nofollow">7,659,161</a></td>
<td valign="top">Methods of forming storage nodes for a DRAM array</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,152" target="_blank" rel="nofollow">7,659,152</a></td>
<td valign="top">Localized biasing for silicon on insulator structures</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,659,151" target="_blank" rel="nofollow">7,659,151</a></td>
<td valign="top">Flip chip with interposer, and methods of making same</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-09-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 04 February 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-04-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-04-february-2010/#comments</comments>
		<pubDate>Thu, 04 Feb 2010 19:24:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7939</guid>
		<description><![CDATA[13 US patent applications published on 04 February 2010 and assigned to Micron



1
20100031129
MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS


2
20100029081
SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES


3
20100029043
PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES


4
20100027368
READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY


5
20100027367
ROW MASK ADDRESSING


6
20100027310
APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS


7
20100027233
MICROELECTRONIC [...]]]></description>
			<content:encoded><![CDATA[<p>13 US patent applications published on 04 February 2010 and assigned to Micron<br />
<span id="more-7939"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100031129.PGNR.&#038;OS=DN/20100031129RS=DN/20100031129" target="_blank">20100031129</a></td>
<td valign="top">MULTIPLE DEVICE APPARATUS, SYSTEMS, AND METHODS</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100029081.PGNR.&#038;OS=DN/20100029081RS=DN/20100029081" target="_blank">20100029081</a></td>
<td valign="top">SINGLE SPACER PROCESS FOR MULTIPLYING PITCH BY A FACTOR GREATER THAN TWO AND RELATED INTERMEDIATE IC STRUCTURES</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100029043.PGNR.&#038;OS=DN/20100029043RS=DN/20100029043" target="_blank">20100029043</a></td>
<td valign="top">PACKAGED MICROELECTRONIC DEVICES AND METHODS FOR MANUFACTURING PACKAGED MICROELECTRONIC DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100027368.PGNR.&#038;OS=DN/20100027368RS=DN/20100027368" target="_blank">20100027368</a></td>
<td valign="top">READ COMMAND TRIGGERED SYNCHRONIZATION CIRCUITRY</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100027367.PGNR.&#038;OS=DN/20100027367RS=DN/20100027367" target="_blank">20100027367</a></td>
<td valign="top">ROW MASK ADDRESSING</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100027310.PGNR.&#038;OS=DN/20100027310RS=DN/20100027310" target="_blank">20100027310</a></td>
<td valign="top">APPARATUS AND METHODS FOR OPTICALLY-COUPLED MEMORY SYSTEMS</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100027233.PGNR.&#038;OS=DN/20100027233RS=DN/20100027233" target="_blank">20100027233</a></td>
<td valign="top">MICROELECTRONIC PACKAGES WITH SMALL FOOTPRINTS AND ASSOCIATED METHODS OF MANUFACTURING</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100026853.PGNR.&#038;OS=DN/20100026853RS=DN/20100026853" target="_blank">20100026853</a></td>
<td valign="top">METHOD AND SYSTEM FOR SYNCHRONIZING A FLASH TO AN IMAGER</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100026533.PGNR.&#038;OS=DN/20100026533RS=DN/20100026533" target="_blank">20100026533</a></td>
<td valign="top">Data Bus Inversion Apparatus, Systems, and Methods</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100026344.PGNR.&#038;OS=DN/20100026344RS=DN/20100026344" target="_blank">20100026344</a></td>
<td valign="top">METHODS, DEVICES, AND SYSTEMS FOR A HIGH VOLTAGE TOLERANT BUFFER</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100025854.PGNR.&#038;OS=DN/20100025854RS=DN/20100025854" target="_blank">20100025854</a></td>
<td valign="top">POLISHING SYSTEMS AND METHODS FOR REMOVING CONDUCTIVE MATERIAL FROM MICROELECTRONIC SUBSTRATES</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100025746.PGNR.&#038;OS=DN/20100025746RS=DN/20100025746" target="_blank">20100025746</a></td>
<td valign="top">METHODS, STRUCTURES AND SYSTEMS FOR INTERCONNECT STRUCTURES IN AN IMAGER SENSOR DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100025362.PGNR.&#038;OS=DN/20100025362RS=DN/20100025362" target="_blank">20100025362</a></td>
<td valign="top">Method of Forming Capacitors</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-04-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 02 February 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-02-february-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-02-february-2010/#comments</comments>
		<pubDate>Tue, 02 Feb 2010 13:57:26 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7898</guid>
		<description><![CDATA[21 US patents granted on 02 February 2010 and assigned to Micron



1
7,657,813
Method and apparatus for generating expect data from a captured bit pattern, and memory device using same


2
7,657,802
Data compression read mode for memory testing


3
7,657,723
System and method for processor with predictive memory retrieval assist


4
7,656,961
Method and apparatus for multi-user transmission


5
7,656,768
Phase masks for use in holographic data storage


6
7,656,745
Circuit, [...]]]></description>
			<content:encoded><![CDATA[<p>21 US patents granted on 02 February 2010 and assigned to Micron<br />
<span id="more-7898"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,813" target="_blank" rel="nofollow">7,657,813</a></td>
<td valign="top">Method and apparatus for generating expect data from a captured bit pattern, and memory device using same</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,802" target="_blank" rel="nofollow">7,657,802</a></td>
<td valign="top">Data compression read mode for memory testing</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,657,723" target="_blank" rel="nofollow">7,657,723</a></td>
<td valign="top">System and method for processor with predictive memory retrieval assist</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,961" target="_blank" rel="nofollow">7,656,961</a></td>
<td valign="top">Method and apparatus for multi-user transmission</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,768" target="_blank" rel="nofollow">7,656,768</a></td>
<td valign="top">Phase masks for use in holographic data storage</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,745" target="_blank" rel="nofollow">7,656,745</a></td>
<td valign="top">Circuit, system and method for controlling read latency</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,740" target="_blank" rel="nofollow">7,656,740</a></td>
<td valign="top">Wordline voltage transfer apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,720" target="_blank" rel="nofollow">7,656,720</a></td>
<td valign="top">Power-off apparatus, systems, and methods</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,709" target="_blank" rel="nofollow">7,656,709</a></td>
<td valign="top">NAND step up voltage switching method</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,209" target="_blank" rel="nofollow">7,656,209</a></td>
<td valign="top">Output slew rate control</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,049" target="_blank" rel="nofollow">7,656,049</a></td>
<td valign="top">CMOS device with asymmetric gate strain</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,012" target="_blank" rel="nofollow">7,656,012</a></td>
<td valign="top">Apparatus for use in semiconductor wafer processing for laterally displacing individual semiconductor devices away from one another</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,656,006" target="_blank" rel="nofollow">7,656,006</a></td>
<td valign="top">Antifuse circuit with well bias transistor</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,973" target="_blank" rel="nofollow">7,655,973</a></td>
<td valign="top">Recessed channel negative differential resistance-based memory cell</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,968" target="_blank" rel="nofollow">7,655,968</a></td>
<td valign="top">Semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,508" target="_blank" rel="nofollow">7,655,508</a></td>
<td valign="top">Overmolding encapsulation process and encapsulated article made therefrom</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,507" target="_blank" rel="nofollow">7,655,507</a></td>
<td valign="top">Microelectronic imaging units and methods of manufacturing microelectronic imaging units</td>
</tr>
<tr>
<td valign="top" align="right">18</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,500" target="_blank" rel="nofollow">7,655,500</a></td>
<td valign="top">Packaged microelectronic devices and methods for packaging microelectronic devices</td>
</tr>
<tr>
<td valign="top" align="right">19</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,387" target="_blank" rel="nofollow">7,655,387</a></td>
<td valign="top">Method to align mask patterns</td>
</tr>
<tr>
<td valign="top" align="right">20</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,384" target="_blank" rel="nofollow">7,655,384</a></td>
<td valign="top">Methods for reducing spherical aberration effects in photolithography</td>
</tr>
<tr>
<td valign="top" align="right">21</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,655,095" target="_blank" rel="nofollow">7,655,095</a></td>
<td valign="top">Method of cleaning semiconductor surfaces</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-02-february-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 28 January 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-28-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-28-january-2010/#comments</comments>
		<pubDate>Thu, 28 Jan 2010 13:17:16 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7858</guid>
		<description><![CDATA[14 US patent applications published on 28 January 2010 and assigned to Micron



1
20100023780
FLASH DEVICE SECURITY METHOD UTILIZING A CHECK REGISTER


2
20100023747
Critical Security Parameter Generation and Exchange System and Method for Smart-Card Memory Modules


3
20100022096
MATERIAL REMOVAL METHODS EMPLOYING SOLUTIONS WITH REVERSIBLE ETCH SELECTIVITIES


4
20100020621
MEMORY DEVICE BIT LINE SENSING SYSTEM AND METHOD THAT COMPENSATES FOR BIT LINE RESISTANCE VARIATIONS


5
20100020609
FLASH MEMORY [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patent applications published on 28 January 2010 and assigned to Micron<br />
<span id="more-7858"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100023780.PGNR.&#038;OS=DN/20100023780RS=DN/20100023780" target="_blank">20100023780</a></td>
<td valign="top">FLASH DEVICE SECURITY METHOD UTILIZING A CHECK REGISTER</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100023747.PGNR.&#038;OS=DN/20100023747RS=DN/20100023747" target="_blank">20100023747</a></td>
<td valign="top">Critical Security Parameter Generation and Exchange System and Method for Smart-Card Memory Modules</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100022096.PGNR.&#038;OS=DN/20100022096RS=DN/20100022096" target="_blank">20100022096</a></td>
<td valign="top">MATERIAL REMOVAL METHODS EMPLOYING SOLUTIONS WITH REVERSIBLE ETCH SELECTIVITIES</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100020621.PGNR.&#038;OS=DN/20100020621RS=DN/20100020621" target="_blank">20100020621</a></td>
<td valign="top">MEMORY DEVICE BIT LINE SENSING SYSTEM AND METHOD THAT COMPENSATES FOR BIT LINE RESISTANCE VARIATIONS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100020609.PGNR.&#038;OS=DN/20100020609RS=DN/20100020609" target="_blank">20100020609</a></td>
<td valign="top">FLASH MEMORY DEVICE WITH REDUNDANT COLUMNS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100020606.PGNR.&#038;OS=DN/20100020606RS=DN/20100020606" target="_blank">20100020606</a></td>
<td valign="top">WORD LINE DRIVERS IN NON-VOLATILE MEMORY DEVICE AND METHOD HAVING A SHARED POWER BANK AND PROCESSOR-BASED SYSTEMS USING SAME</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100020605.PGNR.&#038;OS=DN/20100020605RS=DN/20100020605" target="_blank">20100020605</a></td>
<td valign="top">NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100020247.PGNR.&#038;OS=DN/20100020247RS=DN/20100020247" target="_blank">20100020247</a></td>
<td valign="top">METHOD FOR ASSISTING VIDEO COMPRESSION IN A COMPUTER SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019804.PGNR.&#038;OS=DN/20100019804RS=DN/20100019804" target="_blank">20100019804</a></td>
<td valign="top">ARRAY SENSE AMPLIFIERS, MEMORY DEVICES AND SYSTEMS INCLUDING SAME, AND METHODS OF OPERATION</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019388.PGNR.&#038;OS=DN/20100019388RS=DN/20100019388" target="_blank">20100019388</a></td>
<td valign="top">METHOD FOR AN INTEGRATED CIRCUIT CONTACT</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019298.PGNR.&#038;OS=DN/20100019298RS=DN/20100019298" target="_blank">20100019298</a></td>
<td valign="top">Assemblies Comprising Magnetic Elements And Magnetic Barrier Or Shielding</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019294.PGNR.&#038;OS=DN/20100019294RS=DN/20100019294" target="_blank">20100019294</a></td>
<td valign="top">METHOD AND APPARATUS FOR DECREASING STORAGE NODE PARASITIC CHARGE IN ACTIVE PIXEL IMAGE SENSORS</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019291.PGNR.&#038;OS=DN/20100019291RS=DN/20100019291" target="_blank">20100019291</a></td>
<td valign="top">JFET Devices with PIN Gate Stacks and Methods of Making the Same</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100019249.PGNR.&#038;OS=DN/20100019249RS=DN/20100019249" target="_blank">20100019249</a></td>
<td valign="top">JFET Devices with Increased Barrier Height and Methods of Making Same</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-28-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 26 January 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-26-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-26-january-2010/#comments</comments>
		<pubDate>Tue, 26 Jan 2010 15:48:10 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7817</guid>
		<description><![CDATA[8 US patents granted on 26 January 2010 and assigned to Micron



1
7,652,703
Dual panel pixel readout in an imager


2
7,652,669
Animation packager for an on-line book


3
7,652,495
Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using such pusher assemblies


4
7,652,365
Microelectronic component assemblies and microelectronic component lead frame structures


5
7,651,956
Process for fabricating films of uniform properties [...]]]></description>
			<content:encoded><![CDATA[<p>8 US patents granted on 26 January 2010 and assigned to Micron<br />
<span id="more-7817"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,703" target="_blank" rel="nofollow">7,652,703</a></td>
<td valign="top">Dual panel pixel readout in an imager</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,669" target="_blank" rel="nofollow">7,652,669</a></td>
<td valign="top">Animation packager for an on-line book</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,495" target="_blank" rel="nofollow">7,652,495</a></td>
<td valign="top">Pusher assemblies for use in microfeature device testing, systems with pusher assemblies, and methods for using such pusher assemblies</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,652,365" target="_blank" rel="nofollow">7,652,365</a></td>
<td valign="top">Microelectronic component assemblies and microelectronic component lead frame structures</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,956" target="_blank" rel="nofollow">7,651,956</a></td>
<td valign="top">Process for fabricating films of uniform properties on semiconductor devices</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,951" target="_blank" rel="nofollow">7,651,951</a></td>
<td valign="top">Pitch reduced patterns relative to photolithography features</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,911" target="_blank" rel="nofollow">7,651,911</a></td>
<td valign="top">Memory transistor and methods</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,651,910" target="_blank" rel="nofollow">7,651,910</a></td>
<td valign="top">Methods of forming programmable memory devices</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-26-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 21 January 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-21-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-21-january-2010/#comments</comments>
		<pubDate>Thu, 21 Jan 2010 16:22:21 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7786</guid>
		<description><![CDATA[14 US patent applications published on 21 January 2010 and assigned to Micron



1
20100017778
METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME


2
20100017665
DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE


3
20100015813
GAP PROCESSING


4
20100014805
ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS


5
20100014377
METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS


6
20100014364
MEMORY SYSTEM AND METHOD USING STACKED MEMORY [...]]]></description>
			<content:encoded><![CDATA[<p>14 US patent applications published on 21 January 2010 and assigned to Micron<br />
<span id="more-7786"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100017778.PGNR.&#038;OS=DN/20100017778RS=DN/20100017778" target="_blank">20100017778</a></td>
<td valign="top">METHODS FOR DEFINING EVALUATION POINTS FOR OPTICAL PROXIMITY CORRECTION AND OPTICAL PROXIMITY CORRECTION METHODS INCLUDING SAME</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100017665.PGNR.&#038;OS=DN/20100017665RS=DN/20100017665" target="_blank">20100017665</a></td>
<td valign="top">DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100015813.PGNR.&#038;OS=DN/20100015813RS=DN/20100015813" target="_blank">20100015813</a></td>
<td valign="top">GAP PROCESSING</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100014805.PGNR.&#038;OS=DN/20100014805RS=DN/20100014805" target="_blank">20100014805</a></td>
<td valign="top">ZINC OXIDE DIODES FOR OPTICAL INTERCONNECTIONS</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100014377.PGNR.&#038;OS=DN/20100014377RS=DN/20100014377" target="_blank">20100014377</a></td>
<td valign="top">METHOD AND APPARATUS FOR REDUCING OSCILLATION IN SYNCHRONOUS CIRCUITS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100014364.PGNR.&#038;OS=DN/20100014364RS=DN/20100014364" target="_blank">20100014364</a></td>
<td valign="top">MEMORY SYSTEM AND METHOD USING STACKED MEMORY DEVICE DICE, AND SYSTEM USING THE MEMORY SYSTEM</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100014352.PGNR.&#038;OS=DN/20100014352RS=DN/20100014352" target="_blank">20100014352</a></td>
<td valign="top">NON-VOLATILE MEMORY CELL READ FAILURE REDUCTION</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013512.PGNR.&#038;OS=DN/20100013512RS=DN/20100013512" target="_blank">20100013512</a></td>
<td valign="top">APPARATUS AND METHODS FOR THROUGH SUBSTRATE VIA TEST</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013510.PGNR.&#038;OS=DN/20100013510RS=DN/20100013510" target="_blank">20100013510</a></td>
<td valign="top">SYSTEMS AND METHODS FOR DEFECT TESTING OF EXTERNALLY ACCESSIBLE INTEGRATED CIRCUIT INTERCONNECTS</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013107.PGNR.&#038;OS=DN/20100013107RS=DN/20100013107" target="_blank">20100013107</a></td>
<td valign="top">INTERCONNECT STRUCTURES FOR INTEGRATION OF MULTI-LAYERED INTEGRATED CIRCUIT DEVICES AND METHODS FOR FORMING THE SAME</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013074.PGNR.&#038;OS=DN/20100013074RS=DN/20100013074" target="_blank">20100013074</a></td>
<td valign="top">HIGH DENSITY STACKED DIE ASSEMBLIES, STRUCTURES INCORPORATED THEREIN AND METHODS OF FABRICATING THE ASSEMBLIES</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013061.PGNR.&#038;OS=DN/20100013061RS=DN/20100013061" target="_blank">20100013061</a></td>
<td valign="top">SEMICONDUCTOR STRUCTURES INCLUDING SQUARE CUTS IN SINGLE CRYSTAL SILICON</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100013041.PGNR.&#038;OS=DN/20100013041RS=DN/20100013041" target="_blank">20100013041</a></td>
<td valign="top">MICROELECTRONIC IMAGER PACKAGES WITH COVERS HAVING NON-PLANAR SURFACE FEATURES</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100012922.PGNR.&#038;OS=DN/20100012922RS=DN/20100012922" target="_blank">20100012922</a></td>
<td valign="top">METHODS OF FORMING STRUCTURES INCLUDING NANOTUBES AND STRUCTURES INCLUDING SAME</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-21-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 19 January 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-19-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-19-january-2010/#comments</comments>
		<pubDate>Tue, 19 Jan 2010 15:30:46 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7763</guid>
		<description><![CDATA[13 US patents granted on 19 January 2010 and assigned to Micron



1
7,650,541
Memory block quality identification in a memory device


2
7,649,783
Delayed activation of selected wordlines in memory


3
7,649,316
Assemblies for plasma-enhanced treatment of substrates


4
7,649,201
Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels


5
7,649,145
Compliant spring contact structures


6
7,648,926
Systems and methods for forming metal oxides using metal diketonates and/or [...]]]></description>
			<content:encoded><![CDATA[<p>13 US patents granted on 19 January 2010 and assigned to Micron<br />
<span id="more-7763"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,650,541" target="_blank" rel="nofollow">7,650,541</a></td>
<td valign="top">Memory block quality identification in a memory device</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,783" target="_blank" rel="nofollow">7,649,783</a></td>
<td valign="top">Delayed activation of selected wordlines in memory</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,316" target="_blank" rel="nofollow">7,649,316</a></td>
<td valign="top">Assemblies for plasma-enhanced treatment of substrates</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,201" target="_blank" rel="nofollow">7,649,201</a></td>
<td valign="top">Raised photodiode sensor to increase fill factor and quantum efficiency in scaled pixels</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,649,145" target="_blank" rel="nofollow">7,649,145</a></td>
<td valign="top">Compliant spring contact structures</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,926" target="_blank" rel="nofollow">7,648,926</a></td>
<td valign="top">Systems and methods for forming metal oxides using metal diketonates and/or ketoimines</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,915" target="_blank" rel="nofollow">7,648,915</a></td>
<td valign="top">Methods of forming semiconductor constructions, and methods of recessing materials within openings</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,900" target="_blank" rel="nofollow">7,648,900</a></td>
<td valign="top">Vias having varying diameters and fills for use with a semiconductor device and methods of forming semiconductor device structures including same</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,873" target="_blank" rel="nofollow">7,648,873</a></td>
<td valign="top">Methods of forming capacitors</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,872" target="_blank" rel="nofollow">7,648,872</a></td>
<td valign="top">Methods of forming DRAM arrays</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,856" target="_blank" rel="nofollow">7,648,856</a></td>
<td valign="top">Methods for attaching microfeature dies to external devices</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,648,806" target="_blank" rel="nofollow">7,648,806</a></td>
<td valign="top">Phase shift mask with two-phase clear feature</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,886" target="_blank" rel="nofollow">7,647,886</a></td>
<td valign="top">Systems for depositing material onto workpieces in reaction chambers and methods for removing byproducts from reaction chambers</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-19-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 14 January 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-14-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-14-january-2010/#comments</comments>
		<pubDate>Thu, 14 Jan 2010 14:01:55 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7743</guid>
		<description><![CDATA[7 US patent applications published on 14 January 2010 and assigned to Micron



1
20100009511
PROGRAMMABLE CAPACITOR ASSOCIATED WITH AN INPUT/OUTPUT PAD


2
20100008165
MEMORY CELL SENSING USING NEGATIVE VOLTAGE


3
20100008163
MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS


4
20100008154
INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING


5
20100008144
SYSTEM AND MEMORY FOR SEQUENTIAL MULTI-PLANE PAGE MEMORY OPERATIONS


6
20100007777
Method and apparatus for correcting defective imager pixels


7
20100006428
METHODS AND [...]]]></description>
			<content:encoded><![CDATA[<p>7 US patent applications published on 14 January 2010 and assigned to Micron<br />
<span id="more-7743"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100009511.PGNR.&#038;OS=DN/20100009511RS=DN/20100009511" target="_blank">20100009511</a></td>
<td valign="top">PROGRAMMABLE CAPACITOR ASSOCIATED WITH AN INPUT/OUTPUT PAD</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100008165.PGNR.&#038;OS=DN/20100008165RS=DN/20100008165" target="_blank">20100008165</a></td>
<td valign="top">MEMORY CELL SENSING USING NEGATIVE VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100008163.PGNR.&#038;OS=DN/20100008163RS=DN/20100008163" target="_blank">20100008163</a></td>
<td valign="top">MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100008154.PGNR.&#038;OS=DN/20100008154RS=DN/20100008154" target="_blank">20100008154</a></td>
<td valign="top">INTERCONNECTING BIT LINES IN MEMORY DEVICES FOR MULTIPLEXING</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100008144.PGNR.&#038;OS=DN/20100008144RS=DN/20100008144" target="_blank">20100008144</a></td>
<td valign="top">SYSTEM AND MEMORY FOR SEQUENTIAL MULTI-PLANE PAGE MEMORY OPERATIONS</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100007777.PGNR.&#038;OS=DN/20100007777RS=DN/20100007777" target="_blank">20100007777</a></td>
<td valign="top">Method and apparatus for correcting defective imager pixels</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100006428.PGNR.&#038;OS=DN/20100006428RS=DN/20100006428" target="_blank">20100006428</a></td>
<td valign="top">METHODS AND APPARATUS FOR ELECTROMECHANICALLY AND/OR ELECTROCHEMICALLY-MECHANICALLY REMOVING CONDUCTIVE MATERIAL FROM A MICROELECTRONIC SUBSTRATE</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-14-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 12 January 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-12-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-12-january-2010/#comments</comments>
		<pubDate>Tue, 12 Jan 2010 15:59:09 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7720</guid>
		<description><![CDATA[15 US patents granted on 12 January 2010 and assigned to Micron



1
7,647,569
Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient database processing and storage


2
7,646,654
Distributed write data drivers for burst access memories


3
7,646,407
Digital exposure circuit for an image sensor


4
7,646,229
Method of output slew rate control


5
7,646,213
On-die system and method for controlling termination impedance of memory [...]]]></description>
			<content:encoded><![CDATA[<p>15 US patents granted on 12 January 2010 and assigned to Micron<br />
<span id="more-7720"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,647,569" target="_blank" rel="nofollow">7,647,569</a></td>
<td valign="top">Systems, methods, and computer-readable media for adjusting layout database hierarchies for more efficient database processing and storage</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,654" target="_blank" rel="nofollow">7,646,654</a></td>
<td valign="top">Distributed write data drivers for burst access memories</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,407" target="_blank" rel="nofollow">7,646,407</a></td>
<td valign="top">Digital exposure circuit for an image sensor</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,229" target="_blank" rel="nofollow">7,646,229</a></td>
<td valign="top">Method of output slew rate control</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,213" target="_blank" rel="nofollow">7,646,213</a></td>
<td valign="top">On-die system and method for controlling termination impedance of memory device data bus terminals</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,102" target="_blank" rel="nofollow">7,646,102</a></td>
<td valign="top">Wafer level pre-packaged flip chip systems</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,099" target="_blank" rel="nofollow">7,646,099</a></td>
<td valign="top">Self-aligned, integrated circuit contact</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,075" target="_blank" rel="nofollow">7,646,075</a></td>
<td valign="top">Microelectronic imagers having front side contacts</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,053" target="_blank" rel="nofollow">7,646,053</a></td>
<td valign="top">Memory cell storage node length</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,016" target="_blank" rel="nofollow">7,646,016</a></td>
<td valign="top">Method for automated testing of the modulation transfer function in image sensors</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,646,007" target="_blank" rel="nofollow">7,646,007</a></td>
<td valign="top">Silver-selenide/chalcogenide glass stack for resistance variable memory</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,645,671" target="_blank" rel="nofollow">7,645,671</a></td>
<td valign="top">Recessed access device for a memory</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,645,635" target="_blank" rel="nofollow">7,645,635</a></td>
<td valign="top">Frame structure and semiconductor attach process for use therewith for fabrication of image sensor packages and the like, and resulting packages</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,645,344" target="_blank" rel="nofollow">7,645,344</a></td>
<td valign="top">Method of cleaning semiconductor surfaces</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,853" target="_blank" rel="nofollow">7,644,853</a></td>
<td valign="top">Apparatus for attaching solder balls to BGA package utilizing a tool to pick and dip the solder ball in flux</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-12-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patent applications published on 07 January 2010</title>
		<link>http://www.latestpatents.com/micron-patent-applications-published-on-07-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patent-applications-published-on-07-january-2010/#comments</comments>
		<pubDate>Thu, 07 Jan 2010 14:32:42 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patent Applications]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7698</guid>
		<description><![CDATA[12 US patent applications published on 07 January 2010 and assigned to Micron



1
20100005376
METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES


2
20100005287
DATA SECURITY FOR DIGITAL DATA STORAGE


3
20100005238
MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE


4
20100005217
MULTI-MODE MEMORY DEVICE AND METHOD


5
20100003797
METHOD FOR FORMING TRANSISTOR WITH HIGH BREAKDOWN VOLTAGE


6
20100002530
Memory Address Repair Without Enable Fuses


7
20100002485
CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND [...]]]></description>
			<content:encoded><![CDATA[<p>12 US patent applications published on 07 January 2010 and assigned to Micron<br />
<span id="more-7698"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100005376.PGNR.&#038;OS=DN/20100005376RS=DN/20100005376" target="_blank">20100005376</a></td>
<td valign="top">METHOD AND APPARATUS FOR REPAIRING HIGH CAPACITY/HIGH BANDWIDTH MEMORY DEVICES</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100005287.PGNR.&#038;OS=DN/20100005287RS=DN/20100005287" target="_blank">20100005287</a></td>
<td valign="top">DATA SECURITY FOR DIGITAL DATA STORAGE</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100005238.PGNR.&#038;OS=DN/20100005238RS=DN/20100005238" target="_blank">20100005238</a></td>
<td valign="top">MULTI-SERIAL INTERFACE STACKED-DIE MEMORY ARCHITECTURE</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100005217.PGNR.&#038;OS=DN/20100005217RS=DN/20100005217" target="_blank">20100005217</a></td>
<td valign="top">MULTI-MODE MEMORY DEVICE AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100003797.PGNR.&#038;OS=DN/20100003797RS=DN/20100003797" target="_blank">20100003797</a></td>
<td valign="top">METHOD FOR FORMING TRANSISTOR WITH HIGH BREAKDOWN VOLTAGE</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002530.PGNR.&#038;OS=DN/20100002530RS=DN/20100002530" target="_blank">20100002530</a></td>
<td valign="top">Memory Address Repair Without Enable Fuses</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002485.PGNR.&#038;OS=DN/20100002485RS=DN/20100002485" target="_blank">20100002485</a></td>
<td valign="top">CONFIGURABLE INPUTS AND OUTPUTS FOR MEMORY STACKING SYSTEM AND METHOD</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002314.PGNR.&#038;OS=DN/20100002314RS=DN/20100002314" target="_blank">20100002314</a></td>
<td valign="top">Lens system with symmetrical optics</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002312.PGNR.&#038;OS=DN/20100002312RS=DN/20100002312" target="_blank">20100002312</a></td>
<td valign="top">Over-molded glass lenses and method of forming the same</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002310.PGNR.&#038;OS=DN/20100002310RS=DN/20100002310" target="_blank">20100002310</a></td>
<td valign="top">Extended Depth-of-Field Lenses and Methods For Their Design, Optimization and Manufacturing</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100002094.PGNR.&#038;OS=DN/20100002094RS=DN/20100002094" target="_blank">20100002094</a></td>
<td valign="top">Method and apparatus providing multiple exposure high dynamic range sensor</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20100001789.PGNR.&#038;OS=DN/20100001789RS=DN/20100001789" target="_blank">20100001789</a></td>
<td valign="top">SYSTEMS AND METHODS FOR LOWERING INTERCONNECT CAPACITANCE THROUGH ADJUSTMENT OF RELATIVE SIGNAL LEVELS</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patent-applications-published-on-07-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
		<item>
		<title>Micron patents granted on 05 January 2010</title>
		<link>http://www.latestpatents.com/micron-patents-granted-on-05-january-2010/</link>
		<comments>http://www.latestpatents.com/micron-patents-granted-on-05-january-2010/#comments</comments>
		<pubDate>Tue, 05 Jan 2010 14:32:29 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
				<category><![CDATA[Micron]]></category>
		<category><![CDATA[Patents]]></category>

		<guid isPermaLink="false">http://www.latestpatents.com/?p=7675</guid>
		<description><![CDATA[17 US patents granted on 05 January 2010 and assigned to Micron



1
7,644,253
Memory hub with internal cache and/or memory access prediction


2
7,644,240
Memory device controller


3
7,644,235
Device and method for configuring a cache tag in accordance with burst length


4
7,643,984
Method and system for selecting compatible processors to add to a multiprocessor computer


5
7,643,370
Memory device having conditioning output data


6
7,643,359
Clock generating circuit with multiple [...]]]></description>
			<content:encoded><![CDATA[<p>17 US patents granted on 05 January 2010 and assigned to Micron<br />
<span id="more-7675"></span></p>
<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
<tr>
<td valign="top" align="right">1</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,253" target="_blank" rel="nofollow">7,644,253</a></td>
<td valign="top">Memory hub with internal cache and/or memory access prediction</td>
</tr>
<tr>
<td valign="top" align="right">2</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,240" target="_blank" rel="nofollow">7,644,240</a></td>
<td valign="top">Memory device controller</td>
</tr>
<tr>
<td valign="top" align="right">3</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,644,235" target="_blank" rel="nofollow">7,644,235</a></td>
<td valign="top">Device and method for configuring a cache tag in accordance with burst length</td>
</tr>
<tr>
<td valign="top" align="right">4</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,984" target="_blank" rel="nofollow">7,643,984</a></td>
<td valign="top">Method and system for selecting compatible processors to add to a multiprocessor computer</td>
</tr>
<tr>
<td valign="top" align="right">5</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,370" target="_blank" rel="nofollow">7,643,370</a></td>
<td valign="top">Memory device having conditioning output data</td>
</tr>
<tr>
<td valign="top" align="right">6</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,359" target="_blank" rel="nofollow">7,643,359</a></td>
<td valign="top">Clock generating circuit with multiple modes of operation</td>
</tr>
<tr>
<td valign="top" align="right">7</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,343" target="_blank" rel="nofollow">7,643,343</a></td>
<td valign="top">NAND string with a redundant memory cell</td>
</tr>
<tr>
<td valign="top" align="right">8</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,643,333" target="_blank" rel="nofollow">7,643,333</a></td>
<td valign="top">Process for erasing chalcogenide variable resistance memory bits</td>
</tr>
<tr>
<td valign="top" align="right">9</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,827" target="_blank" rel="nofollow">7,642,827</a></td>
<td valign="top">Apparatus and method for multi-phase clock generation</td>
</tr>
<tr>
<td valign="top" align="right">10</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,651" target="_blank" rel="nofollow">7,642,651</a></td>
<td valign="top">Multi-layer interconnect with isolation layer</td>
</tr>
<tr>
<td valign="top" align="right">11</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,643" target="_blank" rel="nofollow">7,642,643</a></td>
<td valign="top">Apparatus for molding a semiconductor die package with enhanced thermal conductivity</td>
</tr>
<tr>
<td valign="top" align="right">12</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,616" target="_blank" rel="nofollow">7,642,616</a></td>
<td valign="top">Tunnel and gate oxide comprising nitrogen for use with a semiconductor device and a process for forming the device</td>
</tr>
<tr>
<td valign="top" align="right">13</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,591" target="_blank" rel="nofollow">7,642,591</a></td>
<td valign="top">Multi-resistive integrated circuit memory</td>
</tr>
<tr>
<td valign="top" align="right">14</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,550" target="_blank" rel="nofollow">7,642,550</a></td>
<td valign="top">Multi-layer structures for parameter measurement</td>
</tr>
<tr>
<td valign="top" align="right">15</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,204" target="_blank" rel="nofollow">7,642,204</a></td>
<td valign="top">Methods of forming fluorine doped insulating materials</td>
</tr>
<tr>
<td valign="top" align="right">16</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,196" target="_blank" rel="nofollow">7,642,196</a></td>
<td valign="top">Semiconductor fabrication processes</td>
</tr>
<tr>
<td valign="top" align="right">17</td>
<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,642,157" target="_blank" rel="nofollow">7,642,157</a></td>
<td valign="top">Method for enhancing electrode surface area in DRAM cell capacitors</td>
</tr>
</table>
]]></content:encoded>
			<wfw:commentRss>http://www.latestpatents.com/micron-patents-granted-on-05-january-2010/feed/</wfw:commentRss>
		<slash:comments>0</slash:comments>
		</item>
	</channel>
</rss>
