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<channel>
	<title>Latest Patents</title>
	<link>http://www.latestpatents.com</link>
	<description>Latest Patents of Leading Technology Companies</description>
	<pubDate>Thu, 20 Nov 2008 15:30:28 +0000</pubDate>
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		<item>
		<title>Micron patent applications published on 20 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/20/micron-patent-applications-published-on-20-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/20/micron-patent-applications-published-on-20-november-2008/#comments</comments>
		<pubDate>Thu, 20 Nov 2008 15:26:18 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/20/micron-patent-applications-published-on-20-november-2008/</guid>
		<description><![CDATA[	11 US patent applications published on 20 November 2008 and assigned to Micron

	
	
	1
	20080288697
	Memory module having a cover pivotally coupled thereto
	
	
	2
	20080286659
	Extensions of Self-Assembled Structures to Increased Dimensions via a &#8220;Bootstrap&#8221; Self-Templating Method
	
	
	3
	20080285369
	BLOCK ERASE FOR VOLATILE MEMORY
	
	
	4
	20080285341
	READING NON-VOLATILE MULTILEVEL MEMORY CELLS
	
	
	5
	20080284996
	OPTICAL COMPENSATION DEVICES, SYSTEMS, AND METHODS
	
	
	6
	20080284879
	Methods and apparatuses for vignetting correction in image signals
	
	
	7
	20080284465
	On-die system and method [...]]]></description>
			<content:encoded><![CDATA[	<p>11 US patent applications published on 20 November 2008 and assigned to Micron<br />
<a id="more-5260"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080288697.PGNR.&#038;OS=DN/20080288697RS=DN/20080288697" target="_blank">20080288697</a></td>
	<td valign="top">Memory module having a cover pivotally coupled thereto</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080286659.PGNR.&#038;OS=DN/20080286659RS=DN/20080286659" target="_blank">20080286659</a></td>
	<td valign="top">Extensions of Self-Assembled Structures to Increased Dimensions via a &#8220;Bootstrap&#8221; Self-Templating Method</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080285369.PGNR.&#038;OS=DN/20080285369RS=DN/20080285369" target="_blank">20080285369</a></td>
	<td valign="top">BLOCK ERASE FOR VOLATILE MEMORY</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080285341.PGNR.&#038;OS=DN/20080285341RS=DN/20080285341" target="_blank">20080285341</a></td>
	<td valign="top">READING NON-VOLATILE MULTILEVEL MEMORY CELLS</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080284996.PGNR.&#038;OS=DN/20080284996RS=DN/20080284996" target="_blank">20080284996</a></td>
	<td valign="top">OPTICAL COMPENSATION DEVICES, SYSTEMS, AND METHODS</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080284879.PGNR.&#038;OS=DN/20080284879RS=DN/20080284879" target="_blank">20080284879</a></td>
	<td valign="top">Methods and apparatuses for vignetting correction in image signals</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080284465.PGNR.&#038;OS=DN/20080284465RS=DN/20080284465" target="_blank">20080284465</a></td>
	<td valign="top">On-die system and method for controlling termination impedance of memory device data bus terminals</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080284000.PGNR.&#038;OS=DN/20080284000RS=DN/20080284000" target="_blank">20080284000</a></td>
	<td valign="top">Integrated Circuit Packages, Methods of Forming Integrated Circuit Packages, And Methods of Assembling Integrated Circuit Packages</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080283940.PGNR.&#038;OS=DN/20080283940RS=DN/20080283940" target="_blank">20080283940</a></td>
	<td valign="top">LOW-TEMPERATURE GROWN HIGH QUALITY ULTRA-THIN CoTiO3 GATE DIELECTRICS</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080283830.PGNR.&#038;OS=DN/20080283830RS=DN/20080283830" target="_blank">20080283830</a></td>
	<td valign="top">Zinc-tin oxide thin-film transistors</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080283815.PGNR.&#038;OS=DN/20080283815RS=DN/20080283815" target="_blank">20080283815</a></td>
	<td valign="top">Variable resistance memory device having reduced bottom contact area and method of forming the same</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 18 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/18/micron-patents-granted-on-18-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/18/micron-patents-granted-on-18-november-2008/#comments</comments>
		<pubDate>Tue, 18 Nov 2008 13:23:10 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/11/18/micron-patents-granted-on-18-november-2008/</guid>
		<description><![CDATA[	23 US patents granted on 18 November 2008 and assigned to Micron

	
	
	1
	7,454,671
	Memory device testing system and method having real time redundancy repair analysis
	
	
	2
	7,454,646
	Efficient clocking scheme for ultra high-speed systems
	
	
	3
	7,454,593
	Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect
	
	
	4
	7,454,558
	Non-volatile memory with erase block state indication in data section
	
	
	5
	7,454,549
	Systems and [...]]]></description>
			<content:encoded><![CDATA[	<p>23 US patents granted on 18 November 2008 and assigned to Micron<br />
<a id="more-5240"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,671" target="_blank" rel="nofollow">7,454,671</a></td>
	<td valign="top">Memory device testing system and method having real time redundancy repair analysis</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,646" target="_blank" rel="nofollow">7,454,646</a></td>
	<td valign="top">Efficient clocking scheme for ultra high-speed systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,593" target="_blank" rel="nofollow">7,454,593</a></td>
	<td valign="top">Row and column enable signal activation of processing array elements with interconnection logic to simulate bus effect</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,558" target="_blank" rel="nofollow">7,454,558</a></td>
	<td valign="top">Non-volatile memory with erase block state indication in data section</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,549" target="_blank" rel="nofollow">7,454,549</a></td>
	<td valign="top">Systems and methods for performing a hot input function</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,454,451" target="_blank" rel="nofollow">7,454,451</a></td>
	<td valign="top">Method for finding local extrema of a set of values for a parallel processing element</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,751" target="_blank" rel="nofollow">7,453,751</a></td>
	<td valign="top">Sample and hold memory sense amplifier</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,746" target="_blank" rel="nofollow">7,453,746</a></td>
	<td valign="top">Reconstruction of signal timing in integrated circuits</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,737" target="_blank" rel="nofollow">7,453,737</a></td>
	<td valign="top">Program method with optimized voltage level for flash memory</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,723" target="_blank" rel="nofollow">7,453,723</a></td>
	<td valign="top">Memory with weighted multi-page read</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,718" target="_blank" rel="nofollow">7,453,718</a></td>
	<td valign="top">Digital data apparatuses and digital data operational methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,152" target="_blank" rel="nofollow">7,453,152</a></td>
	<td valign="top">Device having reduced chemical mechanical planarization</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,134" target="_blank" rel="nofollow">7,453,134</a></td>
	<td valign="top">Integrated circuit device with a circuit element formed on an active region having rounded corners</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,115" target="_blank" rel="nofollow">7,453,115</a></td>
	<td valign="top">Dielectric relaxation memory</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,112" target="_blank" rel="nofollow">7,453,112</a></td>
	<td valign="top">Integrated circuit memory cells and methods of forming</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,103" target="_blank" rel="nofollow">7,453,103</a></td>
	<td valign="top">Semiconductor constructions</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,453,082" target="_blank" rel="nofollow">7,453,082</a></td>
	<td valign="top">Small electrode for a chalcogenide switching device and method for fabricating same</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,816" target="_blank" rel="nofollow">7,452,816</a></td>
	<td valign="top">Semiconductor processing method and chemical mechanical polishing methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,770" target="_blank" rel="nofollow">7,452,770</a></td>
	<td valign="top">Reduced cell-to-cell shorting for memory arrays</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,766" target="_blank" rel="nofollow">7,452,766</a></td>
	<td valign="top">Finned memory cells and the fabrication thereof</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,760" target="_blank" rel="nofollow">7,452,760</a></td>
	<td valign="top">Thin film transistors and semiconductor constructions</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,759" target="_blank" rel="nofollow">7,452,759</a></td>
	<td valign="top">Carbon nanotube field effect transistor and methods for making same</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,452,732" target="_blank" rel="nofollow">7,452,732</a></td>
	<td valign="top">Comparing identifying indicia formed using laser marking techniques to an identifying indicia model</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 13 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/13/micron-patent-applications-published-on-13-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/13/micron-patent-applications-published-on-13-november-2008/#comments</comments>
		<pubDate>Thu, 13 Nov 2008 14:17:49 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/13/micron-patent-applications-published-on-13-november-2008/</guid>
		<description><![CDATA[	14 US patent applications published on 13 November 2008 and assigned to Micron

	
	
	1
	20080282060
	ACTIVE MEMORY COMMAND ENGINE AND METHOD
	
	
	2
	20080280560
	METHOD AND SYSTEM OF PLACING A RFID TAG IN A CONTINUOUS TRANSMISSION MODE
	
	
	3
	20080280455
	ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING METAL BETA-DIKETIMINATE COMPOUNDS
	
	
	4
	20080280396
	STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE
	
	
	5
	20080279471
	Methods, apparatuses and systems for piecewise generation [...]]]></description>
			<content:encoded><![CDATA[	<p>14 US patent applications published on 13 November 2008 and assigned to Micron<br />
<a id="more-5220"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080282060.PGNR.&#038;OS=DN/20080282060RS=DN/20080282060" target="_blank">20080282060</a></td>
	<td valign="top">ACTIVE MEMORY COMMAND ENGINE AND METHOD</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080280560.PGNR.&#038;OS=DN/20080280560RS=DN/20080280560" target="_blank">20080280560</a></td>
	<td valign="top">METHOD AND SYSTEM OF PLACING A RFID TAG IN A CONTINUOUS TRANSMISSION MODE</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080280455.PGNR.&#038;OS=DN/20080280455RS=DN/20080280455" target="_blank">20080280455</a></td>
	<td valign="top">ATOMIC LAYER DEPOSITION SYSTEMS AND METHODS INCLUDING METAL BETA-DIKETIMINATE COMPOUNDS</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080280396.PGNR.&#038;OS=DN/20080280396RS=DN/20080280396" target="_blank">20080280396</a></td>
	<td valign="top">STACKED DIE PACKAGE FOR PERIPHERAL AND CENTER DEVICE PAD LAYOUT DEVICE</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080279471.PGNR.&#038;OS=DN/20080279471RS=DN/20080279471" target="_blank">20080279471</a></td>
	<td valign="top">Methods, apparatuses and systems for piecewise generation of pixel correction values for image processing</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080279254.PGNR.&#038;OS=DN/20080279254RS=DN/20080279254" target="_blank">20080279254</a></td>
	<td valign="top">SEMICONDUCTOR TEMPERATURE SENSOR WITH HIGH SENSITIVITY</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080279022.PGNR.&#038;OS=DN/20080279022RS=DN/20080279022" target="_blank">20080279022</a></td>
	<td valign="top">SEMICONDUCTOR DEVICE WITH SELF REFRESH TEST MODE</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080278820.PGNR.&#038;OS=DN/20080278820RS=DN/20080278820" target="_blank">20080278820</a></td>
	<td valign="top">TETRAFORM MICROLENSES AND METHOD OF FORMING THE SAME</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080278700.PGNR.&#038;OS=DN/20080278700RS=DN/20080278700" target="_blank">20080278700</a></td>
	<td valign="top">SUB-RESOLUTION ASSIST DEVICES AND METHODS</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080278613.PGNR.&#038;OS=DN/20080278613RS=DN/20080278613" target="_blank">20080278613</a></td>
	<td valign="top">Methods, apparatuses and systems providing pixel value adjustment for images produced with varying focal length lenses</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080278610.PGNR.&#038;OS=DN/20080278610RS=DN/20080278610" target="_blank">20080278610</a></td>
	<td valign="top">Configurable pixel array system and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080277799.PGNR.&#038;OS=DN/20080277799RS=DN/20080277799" target="_blank">20080277799</a></td>
	<td valign="top">LOW TEMPERATURE METHODS OF FORMING BACK SIDE REDISTRIBUTION LAYERS IN ASSOCIATION WITH THROUGH WAFER INTERCONNECTS,  SEMICONDUCTOR DEVICES INCLUDING SAME, AND ASSEMBLIES</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080277734.PGNR.&#038;OS=DN/20080277734RS=DN/20080277734" target="_blank">20080277734</a></td>
	<td valign="top">IMPLANTATION PROCESSES FOR STRAINING TRANSISTOR CHANNELS OF SEMICONDUCTOR DEVICE STRUCTURES AND SEMICONDUCTOR DEVICES WITH STRAINED TRANSISTOR CHANNELS</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080277693.PGNR.&#038;OS=DN/20080277693RS=DN/20080277693" target="_blank">20080277693</a></td>
	<td valign="top">IMAGER ELEMENT, DEVICE AND SYSTEM WITH RECESSED TRANSFER GATE</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 11 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/11/micron-patents-granted-on-11-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/11/micron-patents-granted-on-11-november-2008/#comments</comments>
		<pubDate>Tue, 11 Nov 2008 23:54:22 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/11/11/micron-patents-granted-on-11-november-2008/</guid>
		<description><![CDATA[	19 US patents granted on 11 November 2008 and assigned to Micron

	
	
	1
	D580,434
	Mobile card reader
	
	
	2
	7,451,343
	System and method for communicating a software-generated pulse waveform between two servers in a network
	
	
	3
	7,450,465
	Read command triggered synchronization circuitry
	
	
	4
	7,450,462
	System and memory for sequential multi-plane page memory operations
	
	
	5
	7,450,450
	Circuitry for a programmable element
	
	
	6
	7,450,447
	Memory device and method having low-power, high write latency mode and high-power, [...]]]></description>
			<content:encoded><![CDATA[	<p>19 US patents granted on 11 November 2008 and assigned to Micron<br />
<a id="more-5200"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=D580,434" target="_blank" rel="nofollow">D580,434</a></td>
	<td valign="top">Mobile card reader</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,451,343" target="_blank" rel="nofollow">7,451,343</a></td>
	<td valign="top">System and method for communicating a software-generated pulse waveform between two servers in a network</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,465" target="_blank" rel="nofollow">7,450,465</a></td>
	<td valign="top">Read command triggered synchronization circuitry</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,462" target="_blank" rel="nofollow">7,450,462</a></td>
	<td valign="top">System and memory for sequential multi-plane page memory operations</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,450" target="_blank" rel="nofollow">7,450,450</a></td>
	<td valign="top">Circuitry for a programmable element</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,447" target="_blank" rel="nofollow">7,450,447</a></td>
	<td valign="top">Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,425" target="_blank" rel="nofollow">7,450,425</a></td>
	<td valign="top">Non-volatile memory cell read failure reduction</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,422" target="_blank" rel="nofollow">7,450,422</a></td>
	<td valign="top">NAND architecture memory devices and operation</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,450,410" target="_blank" rel="nofollow">7,450,410</a></td>
	<td valign="top">High speed data bus</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,953" target="_blank" rel="nofollow">7,449,953</a></td>
	<td valign="top">Input buffer design using common-mode feedback (CMFB)</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,941" target="_blank" rel="nofollow">7,449,941</a></td>
	<td valign="top">Master bias current generating circuit with decreased sensitivity to silicon process variation</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,939" target="_blank" rel="nofollow">7,449,939</a></td>
	<td valign="top">Bias generator with feedback control</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,910" target="_blank" rel="nofollow">7,449,910</a></td>
	<td valign="top">Test system for semiconductor components having conductive spring contacts</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,766" target="_blank" rel="nofollow">7,449,766</a></td>
	<td valign="top">Methods of forming a contact opening in a semiconductor assembly using a disposable hard mask</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,736" target="_blank" rel="nofollow">7,449,736</a></td>
	<td valign="top">Pixel with transfer gate with no isolation edge</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,410" target="_blank" rel="nofollow">7,449,410</a></td>
	<td valign="top">Methods of forming CoSi.sub.2, methods of forming field effect transistors, and methods of forming conductive contacts</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,391" target="_blank" rel="nofollow">7,449,391</a></td>
	<td valign="top">Methods of forming plurality of capacitor devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,390" target="_blank" rel="nofollow">7,449,390</a></td>
	<td valign="top">Methods of forming memory</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,449,368" target="_blank" rel="nofollow">7,449,368</a></td>
	<td valign="top">Technique for attaching die to leads</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 06 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/06/micron-patent-applications-published-on-06-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/06/micron-patent-applications-published-on-06-november-2008/#comments</comments>
		<pubDate>Thu, 06 Nov 2008 13:45:48 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/11/06/micron-patent-applications-published-on-06-november-2008/</guid>
		<description><![CDATA[	10 US patent applications published on 06 November 2008 and assigned to Micron

	
	
	1
	20080274625
	METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS
	
	
	2
	20080274413
	Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
	
	
	3
	20080273389
	Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings
	
	
	4
	20080273385
	NAND step up voltage switching method
	
	
	5
	20080273106
	Class AB [...]]]></description>
			<content:encoded><![CDATA[	<p>10 US patent applications published on 06 November 2008 and assigned to Micron<br />
<a id="more-5180"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080274625.PGNR.&#038;OS=DN/20080274625RS=DN/20080274625" target="_blank">20080274625</a></td>
	<td valign="top">METHODS OF FORMING ELECTRONIC DEVICES CONTAINING Zr-Sn-Ti-O FILMS</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080274413.PGNR.&#038;OS=DN/20080274413RS=DN/20080274413" target="_blank">20080274413</a></td>
	<td valign="top">Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080273389.PGNR.&#038;OS=DN/20080273389RS=DN/20080273389" target="_blank">20080273389</a></td>
	<td valign="top">Flash memory cells, NAND cell units, methods of forming NAND cell units, and methods of programming NAND cell unit strings</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080273385.PGNR.&#038;OS=DN/20080273385RS=DN/20080273385" target="_blank">20080273385</a></td>
	<td valign="top">NAND step up voltage switching method</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080273106.PGNR.&#038;OS=DN/20080273106RS=DN/20080273106" target="_blank">20080273106</a></td>
	<td valign="top">Class AB amplifier and imagers and systems using same</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080272845.PGNR.&#038;OS=DN/20080272845RS=DN/20080272845" target="_blank">20080272845</a></td>
	<td valign="top">OPERATIONAL TRANSCONDUCTANCE AMPLIFIER (OTA)</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080272497.PGNR.&#038;OS=DN/20080272497RS=DN/20080272497" target="_blank">20080272497</a></td>
	<td valign="top">METHODS OF FORMING CONDUCTIVE VIAS THROUGH SUBSTRATES, AND STRUCTURES AND ASSEMBLIES RESULTING THEREFROM</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080272478.PGNR.&#038;OS=DN/20080272478RS=DN/20080272478" target="_blank">20080272478</a></td>
	<td valign="top">Circuit and method for interconnecting stacked integrated circuit dies</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080272466.PGNR.&#038;OS=DN/20080272466RS=DN/20080272466" target="_blank">20080272466</a></td>
	<td valign="top">SEMICONDUCTOR SUBSTRATES INCLUDING VIAS OF NONUNIFORM CROSS SECTION AND ASSOCIATED STRUCTURES</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080272421.PGNR.&#038;OS=DN/20080272421RS=DN/20080272421" target="_blank">20080272421</a></td>
	<td valign="top">METHODS, CONSTRUCTIONS, AND DEVICES INCLUDING TANTALUM OXIDE LAYERS</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 04 November 2008</title>
		<link>http://www.latestpatents.com/2008/11/04/micron-patents-granted-on-04-november-2008/</link>
		<comments>http://www.latestpatents.com/2008/11/04/micron-patents-granted-on-04-november-2008/#comments</comments>
		<pubDate>Tue, 04 Nov 2008 11:34:02 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/11/04/micron-patents-granted-on-04-november-2008/</guid>
		<description><![CDATA[	29 US patents granted on 04 November 2008 and assigned to Micron

	
	
	1
	7,448,038
	Method for using filtering to load balance a loop of parallel processing elements
	
	
	2
	7,447,974
	Memory controller method and system compensating for memory cell data losses
	
	
	3
	7,447,973
	Memory controller method and system compensating for memory cell data losses
	
	
	4
	7,447,847
	Memory device trims
	
	
	5
	7,447,720
	Method for finding global extrema of a set of bytes [...]]]></description>
			<content:encoded><![CDATA[	<p>29 US patents granted on 04 November 2008 and assigned to Micron<br />
<a id="more-5160"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,448,038" target="_blank" rel="nofollow">7,448,038</a></td>
	<td valign="top">Method for using filtering to load balance a loop of parallel processing elements</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,974" target="_blank" rel="nofollow">7,447,974</a></td>
	<td valign="top">Memory controller method and system compensating for memory cell data losses</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,973" target="_blank" rel="nofollow">7,447,973</a></td>
	<td valign="top">Memory controller method and system compensating for memory cell data losses</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,847" target="_blank" rel="nofollow">7,447,847</a></td>
	<td valign="top">Memory device trims</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,720" target="_blank" rel="nofollow">7,447,720</a></td>
	<td valign="top">Method for finding global extrema of a set of bytes distributed across an array of parallel processing elements</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,240" target="_blank" rel="nofollow">7,447,240</a></td>
	<td valign="top">Method and system for synchronizing communications links in a hub-based memory system</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,106" target="_blank" rel="nofollow">7,447,106</a></td>
	<td valign="top">Delay stage-interweaved analog DLL/PLL</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,447,085" target="_blank" rel="nofollow">7,447,085</a></td>
	<td valign="top">Multilevel driver</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,855" target="_blank" rel="nofollow">7,446,855</a></td>
	<td valign="top">Methods and apparatuses for configuring radiation in microlithographic processing of workpieces using an adjustment structure</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,812" target="_blank" rel="nofollow">7,446,812</a></td>
	<td valign="top">Wide dynamic range operations for imaging</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,807" target="_blank" rel="nofollow">7,446,807</a></td>
	<td valign="top">Imager pixel with capacitance for boosting reset voltage</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,610" target="_blank" rel="nofollow">7,446,610</a></td>
	<td valign="top">Low voltage CMOS differential amplifier</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,580" target="_blank" rel="nofollow">7,446,580</a></td>
	<td valign="top">System and method to improve the efficiency of synchronous mirror delays and delay locked loops</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,415" target="_blank" rel="nofollow">7,446,415</a></td>
	<td valign="top">Method for filling electrically different features</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,393" target="_blank" rel="nofollow">7,446,393</a></td>
	<td valign="top">Co-sputter deposition of metal-doped chalcogenides</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,385" target="_blank" rel="nofollow">7,446,385</a></td>
	<td valign="top">Methods of fabricating optical packages, systems comprising the same, and their uses</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,372" target="_blank" rel="nofollow">7,446,372</a></td>
	<td valign="top">DRAM tunneling access transistor</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,368" target="_blank" rel="nofollow">7,446,368</a></td>
	<td valign="top">Deposition of metal oxide and/or low asymmetrical tunnel barrier interpoly insulators</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,363" target="_blank" rel="nofollow">7,446,363</a></td>
	<td valign="top">Capacitor including a percentage of amorphous dielectric material and a percentage of crystalline dielectric material</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,357" target="_blank" rel="nofollow">7,446,357</a></td>
	<td valign="top">Split trunk pixel layout</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,351" target="_blank" rel="nofollow">7,446,351</a></td>
	<td valign="top">Transistor structures and transistors with a germanium-containing channel</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,277" target="_blank" rel="nofollow">7,446,277</a></td>
	<td valign="top">Method for sorting integrated circuit devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,446,028" target="_blank" rel="nofollow">7,446,028</a></td>
	<td valign="top">Multi-component integrated circuit contacts</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,996" target="_blank" rel="nofollow">7,445,996</a></td>
	<td valign="top">Low resistance peripheral contacts while maintaining DRAM array integrity</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,991" target="_blank" rel="nofollow">7,445,991</a></td>
	<td valign="top">Methods of forming a plurality of capacitors</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,990" target="_blank" rel="nofollow">7,445,990</a></td>
	<td valign="top">Methods of forming a plurality of capacitors</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,973" target="_blank" rel="nofollow">7,445,973</a></td>
	<td valign="top">Transistor surround gate structure with silicon-on-insulator isolation for memory cells, memory arrays, memory devices and systems and methods of forming same</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,445,951" target="_blank" rel="nofollow">7,445,951</a></td>
	<td valign="top">Trench photosensor for a CMOS imager</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,934" target="_blank" rel="nofollow">7,444,934</a></td>
	<td valign="top">Supercritical fluid-assisted direct write for printing integrated circuits</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 30 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/30/micron-patent-applications-published-on-30-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/30/micron-patent-applications-published-on-30-october-2008/#comments</comments>
		<pubDate>Thu, 30 Oct 2008 14:44:00 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/30/micron-patent-applications-published-on-30-october-2008/</guid>
		<description><![CDATA[	9 US patent applications published on 30 October 2008 and assigned to Micron

	
	
	1
	20080270854
	SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL
	
	
	2
	20080268591
	Methods of Forming Capacitors
	
	
	3
	20080268568
	MATERIAL SIDEWALL DEPOSITION METHOD
	
	
	4
	20080266976
	NAND MEMORY DEVICE AND PROGRAMMING METHODS
	
	
	5
	20080266971
	PROGRAMMING A FLASH MEMORY DEVICE
	
	
	6
	20080266953
	SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE
	
	
	7
	20080266444
	Method, apparatus, and system for continuous autofocusing
	
	
	8
	20080266192
	METHODS [...]]]></description>
			<content:encoded><![CDATA[	<p>9 US patent applications published on 30 October 2008 and assigned to Micron<br />
<a id="more-5140"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080270854.PGNR.&#038;OS=DN/20080270854RS=DN/20080270854" target="_blank">20080270854</a></td>
	<td valign="top">SYSTEM AND METHOD FOR RUNNING TEST AND REDUNDANCY ANALYSIS IN PARALLEL</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080268591.PGNR.&#038;OS=DN/20080268591RS=DN/20080268591" target="_blank">20080268591</a></td>
	<td valign="top">Methods of Forming Capacitors</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080268568.PGNR.&#038;OS=DN/20080268568RS=DN/20080268568" target="_blank">20080268568</a></td>
	<td valign="top">MATERIAL SIDEWALL DEPOSITION METHOD</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266976.PGNR.&#038;OS=DN/20080266976RS=DN/20080266976" target="_blank">20080266976</a></td>
	<td valign="top">NAND MEMORY DEVICE AND PROGRAMMING METHODS</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266971.PGNR.&#038;OS=DN/20080266971RS=DN/20080266971" target="_blank">20080266971</a></td>
	<td valign="top">PROGRAMMING A FLASH MEMORY DEVICE</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266953.PGNR.&#038;OS=DN/20080266953RS=DN/20080266953" target="_blank">20080266953</a></td>
	<td valign="top">SINGLE LATCH DATA CIRCUIT IN A MULTIPLE LEVEL CELL NON-VOLATILE MEMORY DEVICE</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266444.PGNR.&#038;OS=DN/20080266444RS=DN/20080266444" target="_blank">20080266444</a></td>
	<td valign="top">Method, apparatus, and system for continuous autofocusing</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080266192.PGNR.&#038;OS=DN/20080266192RS=DN/20080266192" target="_blank">20080266192</a></td>
	<td valign="top">METHODS AND SYSTEMS OF CHANGING ANTENNA POLARIZATION</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080265340.PGNR.&#038;OS=DN/20080265340RS=DN/20080265340" target="_blank">20080265340</a></td>
	<td valign="top">DISPOSABLE PILLARS FOR CONTACT FORMATION</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 28 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/28/micron-patents-granted-on-28-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/28/micron-patents-granted-on-28-october-2008/#comments</comments>
		<pubDate>Tue, 28 Oct 2008 21:19:34 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/10/28/micron-patents-granted-on-28-october-2008/</guid>
		<description><![CDATA[	34 US patents granted on 28 October 2008 and assigned to Micron

	
	
	1
	7,444,579
	Non-systematic coded error correction
	
	
	2
	7,444,559
	Generation of memory test patterns for DLL calibration
	
	
	3
	7,444,550
	System and method for communicating a software-generated pulse waveform between two servers in a network
	
	
	4
	7,444,537
	System and method for communicating a software-generated pulse waveform between two servers in a network
	
	
	5
	7,444,458
	Method for assigning addresses to memory [...]]]></description>
			<content:encoded><![CDATA[	<p>34 US patents granted on 28 October 2008 and assigned to Micron<br />
<a id="more-5120"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,579" target="_blank" rel="nofollow">7,444,579</a></td>
	<td valign="top">Non-systematic coded error correction</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,559" target="_blank" rel="nofollow">7,444,559</a></td>
	<td valign="top">Generation of memory test patterns for DLL calibration</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,550" target="_blank" rel="nofollow">7,444,550</a></td>
	<td valign="top">System and method for communicating a software-generated pulse waveform between two servers in a network</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,537" target="_blank" rel="nofollow">7,444,537</a></td>
	<td valign="top">System and method for communicating a software-generated pulse waveform between two servers in a network</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,458" target="_blank" rel="nofollow">7,444,458</a></td>
	<td valign="top">Method for assigning addresses to memory devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,444,030" target="_blank" rel="nofollow">7,444,030</a></td>
	<td valign="top">Image encoding with dynamic buffer-capacity-level-based compression adjustment</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,761" target="_blank" rel="nofollow">7,443,761</a></td>
	<td valign="top">Loop filtering for fast PLL locking</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,750" target="_blank" rel="nofollow">7,443,750</a></td>
	<td valign="top">Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,749" target="_blank" rel="nofollow">7,443,749</a></td>
	<td valign="top">Switched capacitor DRAM sense amplifier with immunity to mismatch and offsets</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,743" target="_blank" rel="nofollow">7,443,743</a></td>
	<td valign="top">Method and system for improved efficiency of synchronous mirror delays and delay locked loops</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,715" target="_blank" rel="nofollow">7,443,715</a></td>
	<td valign="top">SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,437" target="_blank" rel="nofollow">7,443,437</a></td>
	<td valign="top">Image sensor with a gated storage node linked to transfer gate</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,427" target="_blank" rel="nofollow">7,443,427</a></td>
	<td valign="top">Wide dynamic range linear-and-log active pixel</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,219" target="_blank" rel="nofollow">7,443,219</a></td>
	<td valign="top">Phase interpolation apparatus, systems, and methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,216" target="_blank" rel="nofollow">7,443,216</a></td>
	<td valign="top">Trimmable delay locked loop circuitry with improved initialization characteristics</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,038" target="_blank" rel="nofollow">7,443,038</a></td>
	<td valign="top">Flip-chip image sensor packages</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,032" target="_blank" rel="nofollow">7,443,032</a></td>
	<td valign="top">Memory device with chemical vapor deposition of titanium for titanium silicide contacts</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,022" target="_blank" rel="nofollow">7,443,022</a></td>
	<td valign="top">Board-on-chip packages</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,009" target="_blank" rel="nofollow">7,443,009</a></td>
	<td valign="top">N well implants to separate blocks in a flash memory device</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,443,006" target="_blank" rel="nofollow">7,443,006</a></td>
	<td valign="top">Photon amplification of image sensors</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,979" target="_blank" rel="nofollow">7,442,979</a></td>
	<td valign="top">Reduced cell-to-cell shorting for memory arrays</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,977" target="_blank" rel="nofollow">7,442,977</a></td>
	<td valign="top">Gated field effect devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,976" target="_blank" rel="nofollow">7,442,976</a></td>
	<td valign="top">DRAM cells with vertical transistors</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,970" target="_blank" rel="nofollow">7,442,970</a></td>
	<td valign="top">Active photosensitive structure with buried depletion layer</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,910" target="_blank" rel="nofollow">7,442,910</a></td>
	<td valign="top">High dynamic range cascaded integration pixel cell</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,655" target="_blank" rel="nofollow">7,442,655</a></td>
	<td valign="top">Selective oxidation methods and transistor fabrication methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,643" target="_blank" rel="nofollow">7,442,643</a></td>
	<td valign="top">Methods of forming conductive elements using organometallic layers and flowable, curable conductive materials</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,633" target="_blank" rel="nofollow">7,442,633</a></td>
	<td valign="top">Decoupling capacitor for high frequency noise immunity</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,608" target="_blank" rel="nofollow">7,442,608</a></td>
	<td valign="top">Methods of fabricating a semiconductor device using angled implantation</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,600" target="_blank" rel="nofollow">7,442,600</a></td>
	<td valign="top">Methods of forming threshold voltage implant regions</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,578" target="_blank" rel="nofollow">7,442,578</a></td>
	<td valign="top">Underfill compounds including electrically charged filler elements, microelectronic devices having underfill compounds including electrically charged filler elements, and methods of underfilling micoelectronic devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">32</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,472" target="_blank" rel="nofollow">7,442,472</a></td>
	<td valign="top">Methods of forming reticles</td>
	</tr>
	<tr>
	<td valign="top" align="right">33</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,442,319" target="_blank" rel="nofollow">7,442,319</a></td>
	<td valign="top">Poly etch without separate oxide decap</td>
	</tr>
	<tr>
	<td valign="top" align="right">34</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,949" target="_blank" rel="nofollow">7,441,949</a></td>
	<td valign="top">System and method for providing temperature data from a memory device having a temperature sensor</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 23 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/23/micron-patent-applications-published-on-23-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/23/micron-patent-applications-published-on-23-october-2008/#comments</comments>
		<pubDate>Thu, 23 Oct 2008 15:36:05 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/23/micron-patent-applications-published-on-23-october-2008/</guid>
		<description><![CDATA[	11 US patent applications published on 23 October 2008 and assigned to Micron

	
	
	1
	20080263412
	PROGRAM FAILURE RECOVERY
	
	
	2
	20080263392
	JTAG controlled self-repair after packaging
	
	
	3
	20080262818
	Creation of Clock and Data Simulation Vectors with Periodic Jitter
	
	
	4
	20080261383
	SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES
	
	
	5
	20080261349
	PROTECTIVE COATING FOR PLANARIZATION
	
	
	6
	20080259696
	DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES
	
	
	7
	20080259689
	MIMICKING PROGRAM VERIFY DRAIN RESISTANCE IN A MEMORY DEVICE
	
	
	8
	20080259180
	Methods, systems [...]]]></description>
			<content:encoded><![CDATA[	<p>11 US patent applications published on 23 October 2008 and assigned to Micron<br />
<a id="more-5100"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080263412.PGNR.&#038;OS=DN/20080263412RS=DN/20080263412" target="_blank">20080263412</a></td>
	<td valign="top">PROGRAM FAILURE RECOVERY</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080263392.PGNR.&#038;OS=DN/20080263392RS=DN/20080263392" target="_blank">20080263392</a></td>
	<td valign="top">JTAG controlled self-repair after packaging</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080262818.PGNR.&#038;OS=DN/20080262818RS=DN/20080262818" target="_blank">20080262818</a></td>
	<td valign="top">Creation of Clock and Data Simulation Vectors with Periodic Jitter</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080261383.PGNR.&#038;OS=DN/20080261383RS=DN/20080261383" target="_blank">20080261383</a></td>
	<td valign="top">SEMICONDUCTOR WORKPIECE CARRIERS AND METHODS FOR PROCESSING SEMICONDUCTOR WORKPIECES</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080261349.PGNR.&#038;OS=DN/20080261349RS=DN/20080261349" target="_blank">20080261349</a></td>
	<td valign="top">PROTECTIVE COATING FOR PLANARIZATION</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080259696.PGNR.&#038;OS=DN/20080259696RS=DN/20080259696" target="_blank">20080259696</a></td>
	<td valign="top">DISTRIBUTED WRITE DATA DRIVERS FOR BURST ACCESS MEMORIES</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080259689.PGNR.&#038;OS=DN/20080259689RS=DN/20080259689" target="_blank">20080259689</a></td>
	<td valign="top">MIMICKING PROGRAM VERIFY DRAIN RESISTANCE IN A MEMORY DEVICE</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080259180.PGNR.&#038;OS=DN/20080259180RS=DN/20080259180" target="_blank">20080259180</a></td>
	<td valign="top">Methods, systems and apparatuses for high-quality green imbalance compensation in images</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080258125.PGNR.&#038;OS=DN/20080258125RS=DN/20080258125" target="_blank">20080258125</a></td>
	<td valign="top">Resistive memory cell fabrication methods and devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080258057.PGNR.&#038;OS=DN/20080258057RS=DN/20080258057" target="_blank">20080258057</a></td>
	<td valign="top">Integrated circuit chips, apparatuses for obtaining backscatter data from samples, methods of backscatter analysis, and methods of forming alpha particle emission and detection systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080257187.PGNR.&#038;OS=DN/20080257187RS=DN/20080257187" target="_blank">20080257187</a></td>
	<td valign="top">Methods of forming a stamp, methods of patterning a substrate, and a stamp and a patterning system for same</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 21 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/21/micron-patents-granted-on-21-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/21/micron-patents-granted-on-21-october-2008/#comments</comments>
		<pubDate>Tue, 21 Oct 2008 13:20:50 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/10/21/micron-patents-granted-on-21-october-2008/</guid>
		<description><![CDATA[	31 US patents granted on 21 October 2008 and assigned to Micron

	
	
	1
	7,441,172
	DVI link with parallel test data
	
	
	2
	7,440,860
	Sequential unique marking
	
	
	3
	7,440,344
	Level shifter for low voltage operation
	
	
	4
	7,440,339
	Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation
	
	
	5
	7,440,336
	Memory device having terminals for transferring multiple types of data
	
	
	6
	7,440,332
	Low power multiple bit sense amplifier
	
	
	7
	7,440,321
	Multiple select gate architecture with select gates [...]]]></description>
			<content:encoded><![CDATA[	<p>31 US patents granted on 21 October 2008 and assigned to Micron<br />
<a id="more-5080"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,441,172" target="_blank" rel="nofollow">7,441,172</a></td>
	<td valign="top">DVI link with parallel test data</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,860" target="_blank" rel="nofollow">7,440,860</a></td>
	<td valign="top">Sequential unique marking</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,344" target="_blank" rel="nofollow">7,440,344</a></td>
	<td valign="top">Level shifter for low voltage operation</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,339" target="_blank" rel="nofollow">7,440,339</a></td>
	<td valign="top">Stacked columnar 1T-nMTj MRAM structure and its method of formation and operation</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,336" target="_blank" rel="nofollow">7,440,336</a></td>
	<td valign="top">Memory device having terminals for transferring multiple types of data</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,332" target="_blank" rel="nofollow">7,440,332</a></td>
	<td valign="top">Low power multiple bit sense amplifier</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,321" target="_blank" rel="nofollow">7,440,321</a></td>
	<td valign="top">Multiple select gate architecture with select gates of different lengths</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,317" target="_blank" rel="nofollow">7,440,317</a></td>
	<td valign="top">One transistor SOI non-volatile random access memory cell</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,310" target="_blank" rel="nofollow">7,440,310</a></td>
	<td valign="top">Memory cell with trenched gated thyristor</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,255" target="_blank" rel="nofollow">7,440,255</a></td>
	<td valign="top">Capacitor constructions and methods of forming</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,440,012" target="_blank" rel="nofollow">7,440,012</a></td>
	<td valign="top">Method and apparatus for optimizing image sensor noise and dynamic range</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,752" target="_blank" rel="nofollow">7,439,752</a></td>
	<td valign="top">Methods of providing semiconductor components within sockets</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,598" target="_blank" rel="nofollow">7,439,598</a></td>
	<td valign="top">Microelectronic imaging units</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,594" target="_blank" rel="nofollow">7,439,594</a></td>
	<td valign="top">Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,576" target="_blank" rel="nofollow">7,439,576</a></td>
	<td valign="top">Ultra-thin body vertical tunneling transistor</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,564" target="_blank" rel="nofollow">7,439,564</a></td>
	<td valign="top">Methods of forming capacitor constructions</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,479" target="_blank" rel="nofollow">7,439,479</a></td>
	<td valign="top">Photonic crystal-based filter for use in an image sensor</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,450" target="_blank" rel="nofollow">7,439,450</a></td>
	<td valign="top">Plating buss and a method of use thereof</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,338" target="_blank" rel="nofollow">7,439,338</a></td>
	<td valign="top">Beta-diketiminate ligand sources and metal-containing compounds thereof, and systems and methods including same</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,195" target="_blank" rel="nofollow">7,439,195</a></td>
	<td valign="top">Systems and methods for forming metal oxides using metal compounds containing aminosilane ligands</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,194" target="_blank" rel="nofollow">7,439,194</a></td>
	<td valign="top">Lanthanide doped TiOx dielectric films by plasma oxidation</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,169" target="_blank" rel="nofollow">7,439,169</a></td>
	<td valign="top">Integrated circuit and methods of redistributing bondpad locations</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,158" target="_blank" rel="nofollow">7,439,158</a></td>
	<td valign="top">Strained semiconductor by full wafer bonding</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,157" target="_blank" rel="nofollow">7,439,157</a></td>
	<td valign="top">Isolation trenches for memory devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,155" target="_blank" rel="nofollow">7,439,155</a></td>
	<td valign="top">Isolation techniques for reducing dark current in CMOS image sensors</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,152" target="_blank" rel="nofollow">7,439,152</a></td>
	<td valign="top">Methods of forming a plurality of capacitors</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,140" target="_blank" rel="nofollow">7,439,140</a></td>
	<td valign="top">Formation of standard voltage threshold and low voltage threshold MOSFET devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,138" target="_blank" rel="nofollow">7,439,138</a></td>
	<td valign="top">Method of forming integrated circuitry</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,439,136" target="_blank" rel="nofollow">7,439,136</a></td>
	<td valign="top">Method of forming a layer comprising epitaxial silicon</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,438,632" target="_blank" rel="nofollow">7,438,632</a></td>
	<td valign="top">Method and apparatus for cleaning a web-based chemical mechanical planarization system</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,438,626" target="_blank" rel="nofollow">7,438,626</a></td>
	<td valign="top">Apparatus and method for removing material from microfeature workpieces</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 16 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/16/micron-patent-applications-published-on-16-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/16/micron-patent-applications-published-on-16-october-2008/#comments</comments>
		<pubDate>Thu, 16 Oct 2008 11:02:20 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/16/micron-patent-applications-published-on-16-october-2008/</guid>
		<description><![CDATA[	13 US patent applications published on 16 October 2008 and assigned to Micron

	
	
	1
	20080254637
	Methods for removing photoresist defects and a source gas for same
	
	
	2
	20080254627
	METHOD FOR ADJUSTING FEATURE SIZE AND POSITION
	
	
	3
	20080254571
	System in package (SIP) with dual laminate interposers
	
	
	4
	20080253614
	METHOD AND APPARATUS FOR DISTRIBUTED ANALYSIS OF IMAGES
	
	
	5
	20080253188
	PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY
	
	
	6
	20080253187
	MULTIPLE SELECT GATE ARCHITECTURE
	
	
	7
	20080252759
	Method, [...]]]></description>
			<content:encoded><![CDATA[	<p>13 US patent applications published on 16 October 2008 and assigned to Micron<br />
<a id="more-5060"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080254637.PGNR.&#038;OS=DN/20080254637RS=DN/20080254637" target="_blank">20080254637</a></td>
	<td valign="top">Methods for removing photoresist defects and a source gas for same</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080254627.PGNR.&#038;OS=DN/20080254627RS=DN/20080254627" target="_blank">20080254627</a></td>
	<td valign="top">METHOD FOR ADJUSTING FEATURE SIZE AND POSITION</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080254571.PGNR.&#038;OS=DN/20080254571RS=DN/20080254571" target="_blank">20080254571</a></td>
	<td valign="top">System in package (SIP) with dual laminate interposers</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080253614.PGNR.&#038;OS=DN/20080253614RS=DN/20080253614" target="_blank">20080253614</a></td>
	<td valign="top">METHOD AND APPARATUS FOR DISTRIBUTED ANALYSIS OF IMAGES</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080253188.PGNR.&#038;OS=DN/20080253188RS=DN/20080253188" target="_blank">20080253188</a></td>
	<td valign="top">PROGRAMMING METHOD TO REDUCE GATE COUPLING INTERFERENCE FOR NON-VOLATILE MEMORY</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080253187.PGNR.&#038;OS=DN/20080253187RS=DN/20080253187" target="_blank">20080253187</a></td>
	<td valign="top">MULTIPLE SELECT GATE ARCHITECTURE</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080252759.PGNR.&#038;OS=DN/20080252759RS=DN/20080252759" target="_blank">20080252759</a></td>
	<td valign="top">Method, apparatus and system providing green-green imbalance compensation</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080252379.PGNR.&#038;OS=DN/20080252379RS=DN/20080252379" target="_blank">20080252379</a></td>
	<td valign="top">High slew rate amplifier, analog-to digital converter using same, CMOS imager using the analog-to-digital converter and related methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080251951.PGNR.&#038;OS=DN/20080251951RS=DN/20080251951" target="_blank">20080251951</a></td>
	<td valign="top">USE OF A DUAL TONE RESIST TO FORM PHOTOMASKS AND INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080251887.PGNR.&#038;OS=DN/20080251887RS=DN/20080251887" target="_blank">20080251887</a></td>
	<td valign="top">SERIAL SYSTEM FOR BLOWING ANTIFUSES</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080251871.PGNR.&#038;OS=DN/20080251871RS=DN/20080251871" target="_blank">20080251871</a></td>
	<td valign="top">Semiconductor fabrication method and system</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080251828.PGNR.&#038;OS=DN/20080251828RS=DN/20080251828" target="_blank">20080251828</a></td>
	<td valign="top">ENHANCED ATOMIC LAYER DEPOSITION</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080251699.PGNR.&#038;OS=DN/20080251699RS=DN/20080251699" target="_blank">20080251699</a></td>
	<td valign="top">METHOD AND SYSTEM FOR WAVELENGTH-DEPENDENT IMAGING AND DETECTION USING A HYBRID FILTER</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 14 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/14/micron-patents-granted-on-14-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/14/micron-patents-granted-on-14-october-2008/#comments</comments>
		<pubDate>Tue, 14 Oct 2008 16:07:13 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/10/14/micron-patents-granted-on-14-october-2008/</guid>
		<description><![CDATA[	23 US patents granted on 14 October 2008 and assigned to Micron

	
	
	1
	7,437,729
	Method for load balancing a loop of parallel processing elements
	
	
	2
	7,437,726
	Method for rounding values for a plurality of parallel processing elements
	
	
	3
	7,437,647
	Mode entry circuit and method
	
	
	4
	7,437,632
	Circuits and methods for repairing defects in memory devices
	
	
	5
	7,437,630
	Testing a multibank memory module
	
	
	6
	7,437,625
	Memory with element redundancy
	
	
	7
	7,437,579
	System and method for selective memory [...]]]></description>
			<content:encoded><![CDATA[	<p>23 US patents granted on 14 October 2008 and assigned to Micron<br />
<a id="more-5040"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,729" target="_blank" rel="nofollow">7,437,729</a></td>
	<td valign="top">Method for load balancing a loop of parallel processing elements</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,726" target="_blank" rel="nofollow">7,437,726</a></td>
	<td valign="top">Method for rounding values for a plurality of parallel processing elements</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,647" target="_blank" rel="nofollow">7,437,647</a></td>
	<td valign="top">Mode entry circuit and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,632" target="_blank" rel="nofollow">7,437,632</a></td>
	<td valign="top">Circuits and methods for repairing defects in memory devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,630" target="_blank" rel="nofollow">7,437,630</a></td>
	<td valign="top">Testing a multibank memory module</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,625" target="_blank" rel="nofollow">7,437,625</a></td>
	<td valign="top">Memory with element redundancy</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,437,579" target="_blank" rel="nofollow">7,437,579</a></td>
	<td valign="top">System and method for selective memory module power management</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,708" target="_blank" rel="nofollow">7,436,708</a></td>
	<td valign="top">NAND memory device column charging</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,705" target="_blank" rel="nofollow">7,436,705</a></td>
	<td valign="top">Multiple level cell memory device with single bit per cell, re-mappable memory block</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,442" target="_blank" rel="nofollow">7,436,442</a></td>
	<td valign="top">Low light sensor signal to noise improvement</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,267" target="_blank" rel="nofollow">7,436,267</a></td>
	<td valign="top">Microstrip line dielectric overlay</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,231" target="_blank" rel="nofollow">7,436,231</a></td>
	<td valign="top">Low power and low timing jitter phase-lock loop and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,202" target="_blank" rel="nofollow">7,436,202</a></td>
	<td valign="top">Method and apparatus for calibrating driver impedance</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,067" target="_blank" rel="nofollow">7,436,067</a></td>
	<td valign="top">Methods for forming conductive structures and structures regarding same</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,020" target="_blank" rel="nofollow">7,436,020</a></td>
	<td valign="top">Flash memory with metal-insulator-metal tunneling program and erase</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,436,018" target="_blank" rel="nofollow">7,436,018</a></td>
	<td valign="top">Discrete trap non-volatile multi-functional memory device</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,913" target="_blank" rel="nofollow">7,435,913</a></td>
	<td valign="top">Slanted vias for electrical circuits on circuit boards and other substrates</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,688" target="_blank" rel="nofollow">7,435,688</a></td>
	<td valign="top">Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,641" target="_blank" rel="nofollow">7,435,641</a></td>
	<td valign="top">Low leakage MIM capacitor</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,636" target="_blank" rel="nofollow">7,435,636</a></td>
	<td valign="top">Fabrication of self-aligned gallium arsenide MOSFETs using damascene gate methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,620" target="_blank" rel="nofollow">7,435,620</a></td>
	<td valign="top">Low temperature methods of forming back side redistribution layers in association with through wafer interconnects</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,536" target="_blank" rel="nofollow">7,435,536</a></td>
	<td valign="top">Method to align mask patterns</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,435,324" target="_blank" rel="nofollow">7,435,324</a></td>
	<td valign="top">Noncontact localized electrochemical deposition of metal thin films</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 09 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/09/micron-patent-applications-published-on-09-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/09/micron-patent-applications-published-on-09-october-2008/#comments</comments>
		<pubDate>Thu, 09 Oct 2008 11:30:30 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/09/micron-patent-applications-published-on-09-october-2008/</guid>
		<description><![CDATA[	10 US patent applications published on 09 October 2008 and assigned to Micron

	
	
	1
	20080248653
	Etchant gas and a method for removing material from a late transition metal structure
	
	
	2
	20080248645
	METHOD TO CREATE A METAL PATTERN USING A DAMASCENE-LIKE PROCESS
	
	
	3
	20080248618
	ATOMIC LAYER DEPOSITION OF CeO2/Al2O3 FILMS AS GATE DIELECTRICS
	
	
	4
	20080248597
	Methods for determining a dose of an impurity implanted in a semiconductor substrate [...]]]></description>
			<content:encoded><![CDATA[	<p>10 US patent applications published on 09 October 2008 and assigned to Micron<br />
<a id="more-5020"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080248653.PGNR.&#038;OS=DN/20080248653RS=DN/20080248653" target="_blank">20080248653</a></td>
	<td valign="top">Etchant gas and a method for removing material from a late transition metal structure</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080248645.PGNR.&#038;OS=DN/20080248645RS=DN/20080248645" target="_blank">20080248645</a></td>
	<td valign="top">METHOD TO CREATE A METAL PATTERN USING A DAMASCENE-LIKE PROCESS</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080248618.PGNR.&#038;OS=DN/20080248618RS=DN/20080248618" target="_blank">20080248618</a></td>
	<td valign="top">ATOMIC LAYER DEPOSITION OF CeO2/Al2O3 FILMS AS GATE DIELECTRICS</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080248597.PGNR.&#038;OS=DN/20080248597RS=DN/20080248597" target="_blank">20080248597</a></td>
	<td valign="top">Methods for determining a dose of an impurity implanted in a semiconductor substrate and an apparatus for same</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080247653.PGNR.&#038;OS=DN/20080247653RS=DN/20080247653" target="_blank">20080247653</a></td>
	<td valign="top">Method and apparatus for parallelization of image compression encoders</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080247226.PGNR.&#038;OS=DN/20080247226RS=DN/20080247226" target="_blank">20080247226</a></td>
	<td valign="top">Memory devices having electrodes comprising nanowires, systems including same and methods of forming same</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080246578.PGNR.&#038;OS=DN/20080246578RS=DN/20080246578" target="_blank">20080246578</a></td>
	<td valign="top">OPEN PATTERN INDUCTOR</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080246520.PGNR.&#038;OS=DN/20080246520RS=DN/20080246520" target="_blank">20080246520</a></td>
	<td valign="top">DELAY-LOCKED LOOP (DLL) SYSTEM FOR DETERMINING FORWARD CLOCK PATH DELAY</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080246133.PGNR.&#038;OS=DN/20080246133RS=DN/20080246133" target="_blank">20080246133</a></td>
	<td valign="top">Flip-chip image sensor packages and methods of fabricating the same</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080246066.PGNR.&#038;OS=DN/20080246066RS=DN/20080246066" target="_blank">20080246066</a></td>
	<td valign="top">Optic wafer with reliefs, wafer assembly including same and methods of dicing wafer assembly</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 07 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/07/micron-patents-granted-on-07-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/07/micron-patents-granted-on-07-october-2008/#comments</comments>
		<pubDate>Wed, 08 Oct 2008 03:31:30 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/10/07/micron-patents-granted-on-07-october-2008/</guid>
		<description><![CDATA[	31 US patents granted on 07 October 2008 and assigned to Micron

	
	
	1
	7,434,152
	Multiple-level data compression read mode for memory testing
	
	
	2
	7,434,081
	System and method for read synchronization of memory modules
	
	
	3
	7,433,751
	Sorting a group of integrated circuit devices for those devices requiring special testing
	
	
	4
	7,433,585
	System and method of lens placement
	
	
	5
	7,433,250
	Sense amplifier circuit
	
	
	6
	7,433,249
	Apparatus with equalizing voltage generation circuit and methods of use
	
	
	7
	7,433,248
	System [...]]]></description>
			<content:encoded><![CDATA[	<p>31 US patents granted on 07 October 2008 and assigned to Micron<br />
<a id="more-5000"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,152" target="_blank" rel="nofollow">7,434,152</a></td>
	<td valign="top">Multiple-level data compression read mode for memory testing</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,434,081" target="_blank" rel="nofollow">7,434,081</a></td>
	<td valign="top">System and method for read synchronization of memory modules</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,751" target="_blank" rel="nofollow">7,433,751</a></td>
	<td valign="top">Sorting a group of integrated circuit devices for those devices requiring special testing</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,585" target="_blank" rel="nofollow">7,433,585</a></td>
	<td valign="top">System and method of lens placement</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,250" target="_blank" rel="nofollow">7,433,250</a></td>
	<td valign="top">Sense amplifier circuit</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,249" target="_blank" rel="nofollow">7,433,249</a></td>
	<td valign="top">Apparatus with equalizing voltage generation circuit and methods of use</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,248" target="_blank" rel="nofollow">7,433,248</a></td>
	<td valign="top">System and method for enhanced mode register definitions</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,237" target="_blank" rel="nofollow">7,433,237</a></td>
	<td valign="top">Memory utilizing oxide nanolaminates</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,231" target="_blank" rel="nofollow">7,433,231</a></td>
	<td valign="top">Multiple select gates with non-volatile memory cells</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,433,227" target="_blank" rel="nofollow">7,433,227</a></td>
	<td valign="top">Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication</td>
	</tr>
	<tr>
	<td valign="top" align="right">11</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,968" target="_blank" rel="nofollow">7,432,968</a></td>
	<td valign="top">CMOS image sensor with reduced 1/f noise</td>
	</tr>
	<tr>
	<td valign="top" align="right">12</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,774" target="_blank" rel="nofollow">7,432,774</a></td>
	<td valign="top">Microstrip line dielectric overlay</td>
	</tr>
	<tr>
	<td valign="top" align="right">13</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,604" target="_blank" rel="nofollow">7,432,604</a></td>
	<td valign="top">Semiconductor component and system having thinned, encapsulated dice</td>
	</tr>
	<tr>
	<td valign="top" align="right">14</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,600" target="_blank" rel="nofollow">7,432,600</a></td>
	<td valign="top">System having semiconductor component with multiple stacked dice</td>
	</tr>
	<tr>
	<td valign="top" align="right">15</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,593" target="_blank" rel="nofollow">7,432,593</a></td>
	<td valign="top">Semiconductor package assembly and method for electrically isolating modules</td>
	</tr>
	<tr>
	<td valign="top" align="right">16</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,562" target="_blank" rel="nofollow">7,432,562</a></td>
	<td valign="top">SRAM devices, and electronic systems comprising SRAM devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">17</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,548" target="_blank" rel="nofollow">7,432,548</a></td>
	<td valign="top">Silicon lanthanide oxynitride films</td>
	</tr>
	<tr>
	<td valign="top" align="right">18</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,546" target="_blank" rel="nofollow">7,432,546</a></td>
	<td valign="top">Apparatus having a memory device with floating gate layer grain boundaries with oxidized portions</td>
	</tr>
	<tr>
	<td valign="top" align="right">19</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,540" target="_blank" rel="nofollow">7,432,540</a></td>
	<td valign="top">Dual conversion gain gate and capacitor combination</td>
	</tr>
	<tr>
	<td valign="top" align="right">20</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,491" target="_blank" rel="nofollow">7,432,491</a></td>
	<td valign="top">Pixel with spatially varying sensor positions</td>
	</tr>
	<tr>
	<td valign="top" align="right">21</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,214" target="_blank" rel="nofollow">7,432,214</a></td>
	<td valign="top">Compositions for dissolution of low-k dielectric film, and methods of use</td>
	</tr>
	<tr>
	<td valign="top" align="right">22</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,212" target="_blank" rel="nofollow">7,432,212</a></td>
	<td valign="top">Methods of processing a semiconductor substrate</td>
	</tr>
	<tr>
	<td valign="top" align="right">23</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,197" target="_blank" rel="nofollow">7,432,197</a></td>
	<td valign="top">Methods of patterning photoresist, and methods of forming semiconductor constructions</td>
	</tr>
	<tr>
	<td valign="top" align="right">24</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,166" target="_blank" rel="nofollow">7,432,166</a></td>
	<td valign="top">Methods of forming a nitrogen enriched region</td>
	</tr>
	<tr>
	<td valign="top" align="right">25</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,152" target="_blank" rel="nofollow">7,432,152</a></td>
	<td valign="top">Methods of forming HSG layers and devices</td>
	</tr>
	<tr>
	<td valign="top" align="right">26</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,148" target="_blank" rel="nofollow">7,432,148</a></td>
	<td valign="top">Shallow trench isolation by atomic-level silicon reconstruction</td>
	</tr>
	<tr>
	<td valign="top" align="right">27</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,121" target="_blank" rel="nofollow">7,432,121</a></td>
	<td valign="top">Isolation process and structure for CMOS imagers</td>
	</tr>
	<tr>
	<td valign="top" align="right">28</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,432,025" target="_blank" rel="nofollow">7,432,025</a></td>
	<td valign="top">Methods of forming reticles</td>
	</tr>
	<tr>
	<td valign="top" align="right">29</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,431,966" target="_blank" rel="nofollow">7,431,966</a></td>
	<td valign="top">Atomic layer deposition method of depositing an oxide on a substrate</td>
	</tr>
	<tr>
	<td valign="top" align="right">30</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,431,773" target="_blank" rel="nofollow">7,431,773</a></td>
	<td valign="top">Atomic layer deposition apparatus and method</td>
	</tr>
	<tr>
	<td valign="top" align="right">31</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,431,225" target="_blank" rel="nofollow">7,431,225</a></td>
	<td valign="top">Methods of operating a liquid vaporizer</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patent applications published on 02 October 2008</title>
		<link>http://www.latestpatents.com/2008/10/02/micron-patent-applications-published-on-02-october-2008/</link>
		<comments>http://www.latestpatents.com/2008/10/02/micron-patent-applications-published-on-02-october-2008/#comments</comments>
		<pubDate>Thu, 02 Oct 2008 11:53:41 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Micron</category>
	<category>Patent Applications</category>
		<guid>http://www.latestpatents.com/2008/10/02/micron-patent-applications-published-on-02-october-2008/</guid>
		<description><![CDATA[	10 US patent applications published on 02 October 2008 and assigned to Micron

	
	
	1
	20080242241
	Wireless communications systems, remote communications systems, external device circuits, wireless device communications modification methods, and wireless communications device communications methods
	
	
	2
	20080241386
	Atomic Layer Deposition Methods
	
	
	3
	20080239806
	NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING
	
	
	4
	20080239272
	Reduced lens heating methods, apparatus, and systems
	
	
	5
	20080239116
	Method and apparatus for automatic linear shift parallax correction for multi-array [...]]]></description>
			<content:encoded><![CDATA[	<p>10 US patent applications published on 02 October 2008 and assigned to Micron<br />
<a id="more-4980"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080242241.PGNR.&#038;OS=DN/20080242241RS=DN/20080242241" target="_blank">20080242241</a></td>
	<td valign="top">Wireless communications systems, remote communications systems, external device circuits, wireless device communications modification methods, and wireless communications device communications methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080241386.PGNR.&#038;OS=DN/20080241386RS=DN/20080241386" target="_blank">20080241386</a></td>
	<td valign="top">Atomic Layer Deposition Methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080239806.PGNR.&#038;OS=DN/20080239806RS=DN/20080239806" target="_blank">20080239806</a></td>
	<td valign="top">NON-VOLATILE MULTILEVEL MEMORY CELL PROGRAMMING</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080239272.PGNR.&#038;OS=DN/20080239272RS=DN/20080239272" target="_blank">20080239272</a></td>
	<td valign="top">Reduced lens heating methods, apparatus, and systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">5</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080239116.PGNR.&#038;OS=DN/20080239116RS=DN/20080239116" target="_blank">20080239116</a></td>
	<td valign="top">Method and apparatus for automatic linear shift parallax correction for multi-array image systems</td>
	</tr>
	<tr>
	<td valign="top" align="right">6</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080239111.PGNR.&#038;OS=DN/20080239111RS=DN/20080239111" target="_blank">20080239111</a></td>
	<td valign="top">Method and appratus for dark current compensation of imaging sensors</td>
	</tr>
	<tr>
	<td valign="top" align="right">7</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080238686.PGNR.&#038;OS=DN/20080238686RS=DN/20080238686" target="_blank">20080238686</a></td>
	<td valign="top">METHODS AND SYSTEMS OF DETERMINING PHYSICAL CHARACTERISTICS ASSOCIATED WITH OBJECTS TAGGED WITH RFID TAGS</td>
	</tr>
	<tr>
	<td valign="top" align="right">8</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080238685.PGNR.&#038;OS=DN/20080238685RS=DN/20080238685" target="_blank">20080238685</a></td>
	<td valign="top">METHODS AND SYSTEMS OF DETERMINING PHYSICAL CHARACTERISTICS ASSOCIATED WITH OBJECTS TAGGED WITH RFID TAGS</td>
	</tr>
	<tr>
	<td valign="top" align="right">9</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080238684.PGNR.&#038;OS=DN/20080238684RS=DN/20080238684" target="_blank">20080238684</a></td>
	<td valign="top">Multi-Antenna Element Systems and Related Methods</td>
	</tr>
	<tr>
	<td valign="top" align="right">10</td>
	<td valign="top" align="right"><a href="http://appft1.uspto.gov/netacgi/nph-Parser?Sect1=PTO2&#038;Sect2=HITOFF&#038;p=1&#038;u=%2Fnetahtml%2FPTO%2Fsearch-bool.html&#038;r=1&#038;f=G&#038;l=50&#038;co1=AND&#038;d=PG01&#038;s1=20080237802.PGNR.&#038;OS=DN/20080237802RS=DN/20080237802" target="_blank">20080237802</a></td>
	<td valign="top">STRUCTURES INCLUDING PASSIVATED GERMANIUM</td>
	</tr>
	</table>
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	</item>
		<item>
		<title>Micron patents granted on 30 September 2008</title>
		<link>http://www.latestpatents.com/2008/09/30/micron-patents-granted-on-30-september-2008/</link>
		<comments>http://www.latestpatents.com/2008/09/30/micron-patents-granted-on-30-september-2008/#comments</comments>
		<pubDate>Tue, 30 Sep 2008 13:27:49 +0000</pubDate>
		<dc:creator>Administrator</dc:creator>
		
	<category>Patents</category>
	<category>Micron</category>
		<guid>http://www.latestpatents.com/2008/09/30/micron-patents-granted-on-30-september-2008/</guid>
		<description><![CDATA[	10 US patents granted on 30 September 2008 and assigned to Micron

	
	
	1
	7,430,742
	Method for load balancing a line of parallel processing elements
	
	
	2
	7,430,002
	Digital imaging system and method for adjusting image-capturing parameters using image comparisons
	
	
	3
	7,429,767
	High performance multi-level non-volatile memory device
	
	
	4
	7,429,763
	Memory with strained semiconductor by wafer bonding with misorientation
	
	
	5
	7,429,541
	Method of forming trench isolation in the fabrication of integrated circuitry
	
	
	6
	7,429,536
	Methods [...]]]></description>
			<content:encoded><![CDATA[	<p>10 US patents granted on 30 September 2008 and assigned to Micron<br />
<a id="more-4960"></a></p>
	<table border="2" cellpadding="4" cellspacing="0" style="border-collapse: collapse">
	<tr>
	<td valign="top" align="right">1</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,742" target="_blank" rel="nofollow">7,430,742</a></td>
	<td valign="top">Method for load balancing a line of parallel processing elements</td>
	</tr>
	<tr>
	<td valign="top" align="right">2</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,430,002" target="_blank" rel="nofollow">7,430,002</a></td>
	<td valign="top">Digital imaging system and method for adjusting image-capturing parameters using image comparisons</td>
	</tr>
	<tr>
	<td valign="top" align="right">3</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnumber=7,429,767" target="_blank" rel="nofollow">7,429,767</a></td>
	<td valign="top">High performance multi-level non-volatile memory device</td>
	</tr>
	<tr>
	<td valign="top" align="right">4</td>
	<td valign="top" align="right"><a href="http://patft1.uspto.gov/netacgi/nph-Parser?patentnu