85 US patent applications published on 29 July 2010 and assigned to IBM
| 1 | 20100192224 | SANDBOX WEB NAVIGATION |
| 2 | 20100192221 | System and Method for Automated Data Retrieval Based on Data Placed in Clipboard Memory |
| 3 | 20100192205 | PREVENTING INADVERTENT LOCK-OUT DURING PASSWORD ENTRY DIALOG |
| 4 | 20100192198 | CACHING OF PRIVATE DATA FOR A CONFIGURABLE TIME PERIOD |
| 5 | 20100192197 | Context-Sensitive Confidentiality within Federated Environments |
| 6 | 20100192194 | EXTRACTION OF CODE LEVEL SECURITY SPECIFICATION |
| 7 | 20100192155 | SCHEDULING FOR PARALLEL PROCESSING OF REGIONALLY-CONSTRAINED PLACEMENT PROBLEM |
| 8 | 20100192146 | DEPLOYMENT OF REMOTE PORTLETS INTO A PORTAL |
| 9 | 20100192140 | METHOD FOR PRESENTING CANDIDATE FOR LINK TARGET TO COMPONENT IN WEB APPLICATION, AS WELL AS COMPUTER PROGRAM AND COMPUTER SYSTEM FOR THE SAME |
| 10 | 20100192137 | METHOD AND SYSTEM TO IMPROVE CODE IN VIRTUAL MACHINES |
| 11 | 20100192133 | METHOD AND SYSTEM FOR ANALYZING MEMORY LEAKS OCCURRING IN JAVA VIRTUAL MACHINE DATA STORAGE HEAPS |
| 12 | 20100192131 | USING ATOMIC SETS OF MEMORY LOCATIONS |
| 13 | 20100192123 | Software Development For A Hybrid Computing Environment |
| 14 | 20100192116 | MINTERM TRACING AND REPORTING |
| 15 | 20100192110 | METHOD FOR MAKING A 3-DIMENSIONAL VIRTUAL WORLD ACCESSIBLE FOR THE BLIND |
| 16 | 20100192103 | SPIRALING RADIAL MENUS IN COMPUTER SYSTEMS |
| 17 | 20100192102 | DISPLAYING RADIAL MENUS NEAR EDGES OF A DISPLAY AREA |
| 18 | 20100192101 | DISPLAYING RADIAL MENUS IN A GRAPHICS CONTAINER |
| 19 | 20100192089 | CONTROLLING SCROLLING OF A DOCUMENT |
| 20 | 20100192071 | CLIENT PROGRAM, TERMINAL, METHOD, SERVER SYSTEM AND SERVER PROGRAM |
| 21 | 20100192060 | AUTOMATIC GENERATION OF ASSENT INDICATION IN A DOCUMENT APPROVAL FUNCTION FOR COLLABORATIVE DOCUMENT EDITING |
| 22 | 20100192054 | SEMATICALLY TAGGED BACKGROUND INFORMATION PRESENTATION |
| 23 | 20100192023 | Optimizing Exception and Error Propagation Through Scopes |
| 24 | 20100192014 | PSEUDO RANDOM PROCESS STATE REGISTER FOR FAST RANDOM PROCESS TEST GENERATION |
| 25 | 20100192008 | USING VIRTUAL COPIES IN A FAILOVER AND FAILBACK ENVIRONMENT |
| 26 | 20100192000 | Setting Controller Termination in a Memory Controller and Memory Device Interface in a Communication Bus |
| 27 | 20100191940 | SINGLE STEP MODE IN A SOFTWARE PIPELINE WITHIN A HIGHLY THREADED NETWORK ON A CHIP MICROPROCESSOR |
| 28 | 20100191939 | TRIGONOMETRIC SUMMATION VECTOR EXECUTION UNIT |
| 29 | 20100191937 | Implied Storage Operation Decode Using Redundant Target Address Detection |
| 30 | 20100191925 | DEFERRED VOLUME METADATA INVALIDATION |
| 31 | 20100191923 | Data Processing In A Computing Environment |
| 32 | 20100191922 | DATA STORAGE PERFORMANCE ENHANCEMENT THROUGH A WRITE ACTIVITY LEVEL METRIC RECORDED IN HIGH PERFORMANCE BLOCK STORAGE METADATA |
| 33 | 20100191921 | REGION COHERENCE ARRAY FOR A MULT-PROCESSOR SYSTEM HAVING SUBREGIONS AND SUBREGION PREFETCHING |
| 34 | 20100191917 | Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Watch List Of Currently Registered Virtual Addresses By An Operating System |
| 35 | 20100191916 | Optimizing A Cache Back Invalidation Policy |
| 36 | 20100191915 | SYSTEM AND COMPUTER PROGRAM PRODUCT FOR DYNAMIC QUEUE SPLITTING FOR MAXIMIZING THROUGHPUT OF QUEUE BASED OPERATIONS WHILE MAINTAINING PER-DESTINATION ORDER OF OPERATIONS |
| 37 | 20100191914 | REGION COHERENCE ARRAY HAVING HINT BITS FOR A CLUSTERED SHARED-MEMORY MULTIPROCESSOR SYSTEM |
| 38 | 20100191909 | Administering Registered Virtual Addresses In A Hybrid Computing Environment Including Maintaining A Cache Of Ranges Of Currently Registered Virtual Addresses |
| 39 | 20100191894 | Digital Data Architecture Employing Redundant Links in a Daisy Chain of Component Modules |
| 40 | 20100191843 | Method and System for Selection of a Runtime Stack for Deployment of a Web Service |
| 41 | 20100191823 | Data Processing In A Hybrid Computing Environment |
| 42 | 20100191822 | Broadcasting Data In A Hybrid Computing Environment |
| 43 | 20100191812 | SYSTEM AND METHOD FOR CLIENT-BASED INSTANT MESSAGE MONITORING FOR OFF-LINE USERS |
| 44 | 20100191781 | METHOD FOR OBJECTCLASS VERSIONING |
| 45 | 20100191767 | EXPECTED FUTURE CONDITION SUPPORT IN AN ABSTRACT QUERY ENVIRONMENT |
| 46 | 20100191738 | APPARATUS, SYSTEM, AND METHOD FOR MODIFYING DATA SET NAMES |
| 47 | 20100191711 | Synchronizing Access To Resources In A Hybrid Computing Environment |
| 48 | 20100191708 | Synchronous Deletion of Managed Files |
| 49 | 20100191706 | Storing Information for Dynamically Enlisted Resources in a Transaction |
| 50 | 20100191690 | FRAMEWORK FOR DELTA ANALYSIS DURING AUTOMATED BUILDS |
| 51 | 20100191595 | METHOD, APPARATUS, AND SYSTEM FOR EXCHANGING SERVICES IN A DISTRIBUTED SYSTEM |
| 52 | 20100191531 | QUANTIZING FEATURE VECTORS IN DECISION-MAKING APPLICATIONS |
| 53 | 20100191466 | GPS LOCATION AND FAVORITE PREDICTION BASED ON IN-VEHICLE META-DATA |
| 54 | 20100191385 | SYSTEM FOR PREDICTION AND COMMUNICATION OF ENVIRONMENTALLY INDUCED POWER USEAGE LIMITATION |
| 55 | 20100190526 | Cellular Telephone Using Multiple Accounts |
| 56 | 20100190472 | PHONE NUMBER ENCAPSULATION USING TOKEN BASED FRAMEWORK |
| 57 | 20100190464 | SIMPLE RADIO FREQUENCY INTEGRATED CIRCUIT (RFIC) PACKAGES WITH INTEGRATED ANTENNAS |
| 58 | 20100190430 | AIR PERMEABLE MATERIAL FOR DATA CENTER COOLING |
| 59 | 20100190096 | TARGET AND METHOD FOR MASK-TO-WAFER CD, PATTERN PLACEMENT AND OVERLAY MEASUREMENT AND CONTROL |
| 60 | 20100189111 | STREAMING DIRECT INTER-THREAD COMMUNICATION BUFFER PACKETS THAT SUPPORT HARDWARE CONTROLLED ARBITRARY VECTOR OPERAND ALIGNMENT IN A DENSELY THREADED NETWORK ON A CHIP |
| 61 | 20100188919 | Calibration of Memory Driver With Offset in a Memory Controller and Memory Device Interface in a Communication Bus |
| 62 | 20100188918 | Setting Controller VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
| 63 | 20100188917 | Setting Memory Device Termination in a Memory Device and Memory Controller Interface in a Communication Bus |
| 64 | 20100188916 | Setting Memory Controller Driver to Memory Device Termination Value in a Communication Bus |
| 65 | 20100188908 | Setting Memory Device VREF in a Memory Controller and Memory Device Interface in a Communication Bus |
| 66 | 20100188888 | Implementing Enhanced Dual Mode SRAM Performance Screen Ring Oscillator |
| 67 | 20100188886 | Implementing Enhanced SRAM Stability and Enhanced Chip Yield With Configurable Wordline Voltage Levels |
| 68 | 20100188776 | SYSTEM AND METHOD FOR CLEANING A TAPE DRIVE |
| 69 | 20100188403 | Tree Insertion Depth Adjustment Based on View Frustrum and Distance Culling |
| 70 | 20100188402 | User-Defined Non-Visible Geometry Featuring Ray Filtering |
| 71 | 20100188396 | Updating Ray Traced Acceleration Data Structures Between Frames Based on Changing Perspective |
| 72 | 20100188273 | METHOD AND SYSTEM FOR EFFICIENT DATA TRANSMISSION WITH SERVER SIDE DE-DUPLICATION |
| 73 | 20100188126 | Voltage Controlled Duty Cycle and Non-Overlapping Clock Generation Implementation |
| 74 | 20100187689 | SEMICONDUCTOR CHIPS INCLUDING PASSIVATION LAYER TRENCH STRUCTURE |
| 75 | 20100187643 | METHOD FOR TUNING THE THRESHOLD VOLTAGE OF A METAL GATE AND HIGH-K DEVICE |
| 76 | 20100187641 | HIGH PERFORMANCE MOSFET |
| 77 | 20100187636 | METHOD TO INCREASE STRAIN ENHANCEMENT WITH SPACERLESS FET AND DUAL LINER PROCESS |
| 78 | 20100187614 | SELECTIVE NITRIDATION OF GATE OXIDES |
| 79 | 20100187610 | SEMICONDUCTOR DEVICE HAVING DUAL METAL GATES AND METHOD OF MANUFACTURE |
| 80 | 20100187607 | LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR WAFERS WITH BUILT-IN SHALLOW TRENCH ISOLATION IN BACK GATE LAYER |
| 81 | 20100187592 | HIGH PERFORMANCE FLASH MEMORY DEVICES |
| 82 | 20100187579 | TRANSISTOR DEVICES AND METHODS OF MAKING |
| 83 | 20100187578 | STRESS ENHANCED TRANSISTOR DEVICES AND METHODS OF MAKING |
| 84 | 20100187525 | IMPLEMENTING TAMPER EVIDENT AND RESISTANT DETECTION THROUGH MODULATION OF CAPACITANCE |
| 85 | 20100187126 | ETCHING SYSTEM AND METHOD FOR FORMING MULTIPLE POROUS SEMICONDUCTOR REGIONS WITH DIFFERENT OPTICAL AND STRUCTURAL PROPERTIES ON A SINGLE SEMICONDUCTOR WAFER |