IBM patents granted on 16 June 2015

282 US patents granted on 16 June 2015 and assigned to IBM

1 9,060,457 Sidewalls of electroplated copper interconnects
2 9,060,433 Thermal dissipative retractable flex assembly
3 9,060,428 Coreless multi-layer circuit substrate with minimized pad capacitance
4 9,060,417 Device for attenuating propagation of electromagnetic emissions from an enclosure
5 9,060,414 Solid state storage media cartridge
6 9,060,252 Rate adaptive transmission of wireless broadcast packets
7 9,060,205 Optimizing streaming of a group of videos
8 9,060,203 Personalized categorization of television programming
9 9,060,033 Generation and caching of content in anticipation of presenting content in web conferences
10 9,060,008 Mapping of logical volumes to host clusters
11 9,059,993 System and method for using a same program on a local system and a remote system
12 9,059,973 Securing sensitive information in a network cloud
13 9,059,972 Issuing, presenting and challenging mobile device identification documents
14 9,059,960 Automatically recommending firewall rules during enterprise information technology transformation
15 9,059,951 Method and apparatus for spam message detection
16 9,059,937 Multi-role distributed line card
17 9,059,922 Network traffic distribution
18 9,059,911 Diagnostics in a distributed fabric system
19 9,059,852 Validating a user’s identity utilizing information embedded in a image file
20 9,059,847 Reliable multicast broadcast in wireless networks
21 9,059,744 Encoding a data word for writing the encoded data word in a multi-level solid state memory
22 9,059,731 Boosting decompression in the presence of reoccurring Huffman trees
23 9,059,728 Random extraction from compressed data
24 9,059,707 Quantum circuit within waveguide-beyond-cutoff
25 9,059,679 Tunable interconnect structures, and integrated circuit containing the same
26 9,059,674 Multi-tunable superconducting circuits
27 9,059,660 Variable frequency oscillator with specialized inverter stages
28 9,059,658 Increasing tape velocity by dynamic switching
29 9,059,552 Land grid array (LGA) socket cartridge and method of forming
30 9,059,494 Marchand balun structure and design method
31 9,059,404 Resistive memory with a stabilizer
32 9,059,399 Magnetic materials with enhanced perpendicular anisotropy energy density for STT-RAM
33 9,059,396 Integrated semiconductor devices with single crystalline beam, methods of manufacture and design structure
34 9,059,394 Self-aligned lower bottom electrode
35 9,059,389 Free layers with iron interfacial layer and oxide cap for high perpendicular anisotropy energy density
36 9,059,373 Protecting a thermal sensitive component in a thermal process
37 9,059,360 Photoconductor-on-active pixel device
38 9,059,339 Light emitting diodes with via contact scheme
39 9,059,333 Facilitating chip dicing for metal-metal bonding and hybrid wafer bonding
40 9,059,323 Method of forming fin-field effect transistor (finFET) structure
41 9,059,322 Semiconductor-on-insulator (SOI) deep trench capacitor
42 9,059,321 Buried channel field-effect transistors
43 9,059,320 Structure and method of forming enhanced array device isolation for implanted plate EDRAM
44 9,059,319 Embedded dynamic random access memory device and method
45 9,059,318 Stressed source/drain CMOS and method of forming same
46 9,059,316 Structure and method for mobility enhanced MOSFETs with unalloyed silicide
47 9,059,315 Concurrently forming nFET and pFET gate dielectric layers
48 9,059,314 Structure and method to obtain EOT scaled dielectric stacks
49 9,059,313 Replacement gate having work function at valence band edge
50 9,059,311 CMOS transistors with identical active semiconductor region shapes
51 9,059,308 Method of manufacturing dummy gates of a different material as insulation between adjacent devices
52 9,059,307 Method of implementing buried FET below and beside FinFET on bulk substrate
53 9,059,305 Planar qubits having increased coherence times
54 9,059,292 Source and drain doping profile control employing carbon-doped semiconductor material
55 9,059,291 Semiconductor-on-insulator device including stand-alone well implant to provide junction butting
56 9,059,290 FinFET device formation
57 9,059,289 Stringer-free gate electrode for a suspended semiconductor fin
58 9,059,288 Overlapped III-V finfet with doped semiconductor extensions
59 9,059,287 Semiconductor device including finfet and diode having reduced defects in depletion region
60 9,059,286 Pre-gate, source/drain strain layer formation
61 9,059,285 Structure and method for increasing strain in a device
62 9,059,281 Dual L-shaped drift regions in an LDMOS device and method of making the same
63 9,059,278 High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
64 9,059,276 High voltage laterally diffused metal oxide semiconductor
65 9,059,274 Replacement gate self-aligned carbon nanostructure transistor
66 9,059,272 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
67 9,059,271 Self-aligned III-V MOSFET fabrication with in-situ III-V epitaxy and in-situ metal epitaxy and contact formation
68 9,059,270 Replacement gate MOSFET with raised source and drain
69 9,059,269 Silicon-on-insulator heat sink
70 9,059,267 III-V device with overlapped extension regions using replacement gate
71 9,059,258 Controlled metal extrusion opening in semiconductor structure and method of forming
72 9,059,257 Self-aligned vias formed using sacrificial metal caps
73 9,059,254 Overlay-tolerant via mask and reactive ion etch (RIE) technique
74 9,059,253 Self-aligned contacts for replacement metal gate transistors
75 9,059,252 Silicon waveguide on bulk silicon substrate and methods of forming
76 9,059,251 Microelectronic structure including air gap
77 9,059,250 Lateral-dimension-reducing metallic hard mask etch
78 9,059,249 Interconnect structures containing a photo-patternable low-k dielectric with a curved sidewall surface
79 9,059,248 Junction butting on SOI by raised epitaxial structure and method
80 9,059,245 Semiconductor-on-insulator (SOI) substrates with ultra-thin SOI layers and buried oxides
81 9,059,244 Fabricating shallow-trench isolation semiconductor devices to reduce or eliminate oxygen diffusion
82 9,059,243 Shallow trench isolation structures
83 9,059,242 FinFET semiconductor device having increased gate height control
84 9,059,241 3D assembly for interposer bow
85 9,059,240 Fixture for shaping a laminate substrate
86 9,059,234 Formation of a high aspect ratio trench in a semiconductor substrate and a bipolar semiconductor device having a high aspect ratio trench isolation region
87 9,059,233 Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region
88 9,059,232 T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator
89 9,059,231 T-shaped compound semiconductor lateral bipolar transistor on semiconductor-on-insulator
90 9,059,230 Lateral silicon-on-insulator bipolar junction transistor process and structure
91 9,059,217 FET semiconductor device with low resistance and enhanced metal fill
92 9,059,213 Embedded DRAM for extremely thin semiconductor-on-insulator
93 9,059,212 Back-end transistors with highly doped low-temperature contacts
94 9,059,211 Oxygen scavenging spacer for a gate electrode
95 9,059,209 Replacement gate ETSOI with sharp junction
96 9,059,208 Replacement gate integration scheme employing multiple types of disposable gate structures
97 9,059,207 Strained channel for depleted channel semiconductor devices
98 9,059,206 Epitaxial grown extremely shallow extension region
99 9,059,205 Method of manufacturing a semiconductor device using source/drain epitaxial overgrowth for forming self-aligned contacts without spacer loss and a semiconductor device formed by same
100 9,059,204 Methodology and apparatus for tuning driving current of semiconductor transistors
101 9,059,203 Semiconductor-on-insulator (SOI) structure with selectivity placed sub-insulator layer void(s) and method of forming the SOI structure
102 9,059,198 Bi-directional silicon controlled rectifier structure
103 9,059,196 Bipolar junction transistors with self-aligned terminals
104 9,059,195 Lateral bipolar transistors having partially-depleted intrinsic base
105 9,059,194 High-K and metal filled trench-type EDRAM capacitor with electrode depth and dimension control
106 9,059,191 Chamfered corner crackstop for an integrated circuit chip
107 9,059,190 Measuring current and resistance using combined diodes/resistor structure to monitor integrated circuit manufacturing process variations
108 9,059,188 Graphene resistor based tamper resistant identifier with contactless reading
109 9,059,183 Structure of very high insertion loss of the substrate noise decoupling
110 9,059,180 Thick bond pad for chip with cavity package
111 9,059,177 Doping of copper wiring structures in back end of line processing
112 9,059,176 Copper interconnect with CVD liner and metallic cap
113 9,059,175 Forming BEOL line fuse structure
114 9,059,173 Electronic fuse line with modified cap
115 9,059,171 Electrical fuse and method of making
116 9,059,170 Electronic fuse having a damaged region
117 9,059,169 E-fuse structures and methods of manufacture
118 9,059,167 Structure and method for making crack stop for 3D integrated circuits
119 9,059,166 Interconnect with hybrid metallization
120 9,059,164 Embedded interlevel dielectric barrier layers for replacement metal gate field effect transistors
121 9,059,163 Structure for logic circuit and serializer-deserializer stack
122 9,059,161 Composite wiring board with electrical through connections
123 9,059,139 Raised source/drain and gate portion with dielectric spacer or air gap spacer
124 9,059,138 Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure
125 9,059,135 Nanochannel process and structure for bio-detection
126 9,059,134 Self-aligned contacts for high k/metal gate process flow
127 9,059,132 Self aligned capacitor fabrication
128 9,059,131 Charge breakdown avoidance for MIM elements in SOI base technology and method
129 9,059,130 Phase changing on-chip thermal heat sink
130 9,059,127 Packages for three-dimensional die stacks
131 9,059,123 Active matrix using hybrid integrated circuit and bipolar transistor
132 9,059,120 In-situ relaxation for improved CMOS product lifetime
133 9,059,111 Reliable back-side-metal structure
134 9,059,106 Compensating for warpage of a flip chip package by varying heights of a redistribution layer on an integrated circuit chip
135 9,059,102 Metrology marks for unidirectional grating superposition patterning processes
136 9,059,097 Inhibiting propagation of imperfections in semiconductor devices
137 9,059,096 Method to form silicide contact in trenches
138 9,059,095 Self-aligned borderless contacts using a photo-patternable dielectric material as a replacement contact
139 9,059,091 Transistor having replacement metal gate and process for fabricating the same
140 9,059,080 Methods of fabricating trench generated device structures
141 9,059,075 Selective gallium nitride regrowth on (100) silicon
142 9,059,073 Method for controlled removal of a semiconductor device layer from a base substrate
143 9,059,052 Alternating open-ended via chains for testing via formation and dielectric integrity
144 9,059,051 Inline measurement of through-silicon via depth
145 9,059,044 On-chip diode with fully depleted semiconductor devices
146 9,059,043 Fin field effect transistor with self-aligned source/drain regions
147 9,059,041 Dual channel hybrid semiconductor-on-insulator semiconductor devices
148 9,059,040 Structure and method for reducing floating body effect of SOI MOSFETS
149 9,059,039 Reducing wafer bonding misalignment by varying thermal treatment prior to bonding
150 9,059,031 DRAM with dual level word lines
151 9,059,025 Photonics device and CMOS device having a common gate
152 9,059,021 FinFET device
153 9,059,019 Semiconductor device including source/drain formed on bulk and gate channel formed on oxide layer
154 9,059,017 Source/drain-to-source/drain recessed strap and methods of manufacture of same
155 9,059,016 Lateral heterojunction bipolar transistors
156 9,059,014 Integrated circuit diode
157 9,059,013 Self-formation of high-density arrays of nanostructures
158 9,059,007 Thin-film hybrid complementary circuits
159 9,059,006 Replacement-gate-compatible programmable electrical antifuse
160 9,059,005 MOSFET with recessed channel film and abrupt junctions
161 9,059,002 Non-merged epitaxially grown MOSFET devices
162 9,059,000 Methods and structures for protecting one area while processing another area on a chip
163 9,058,999 Low voltage metal gate antifuse with depletion mode MOSFET
164 9,058,997 Process of multiple exposures with spin castable films
165 9,058,995 Self-protected drain-extended metal-oxide-semiconductor transistor
166 9,058,992 Lateral diode compatible with FinFET and method to fabricate same
167 9,058,990 Controlled spalling of group III nitrides containing an embedded spall releasing plane
168 9,058,987 Rare-earth oxide isolated semiconductor fin
169 9,058,983 In-situ hardmask generation
170 9,058,976 Cleaning composition and process for cleaning semiconductor devices and/or tooling during manufacturing thereof
171 9,058,974 Distorting donor wafer to corresponding distortion of host wafer
172 9,058,973 Passive devices fabricated on glass substrates, methods of manufacture and design structures
173 9,058,903 Methods and circuits for disrupting integrated circuit function
174 9,058,896 DRAM refresh
175 9,058,887 Reprogrammable electrical fuse
176 9,058,868 Piezoelectronic memory
177 9,058,866 SRAM local evaluation logic for column selection
178 9,058,861 Power management SRAM write bit line drive circuit
179 9,058,852 Memory state sensing based on cell capacitance
180 9,058,843 Recovery of data written before initialization of format in tape media
181 9,058,828 Servo pattern of a tape storage medium
182 9,058,669 Incorporating video meta-data in 3D models
183 9,058,597 Determining availability based on percentage available
184 9,058,596 Determining availability based on percentage available
185 9,058,586 Identification of a person located proximite to a contact identified in an electronic communication client
186 9,058,576 Multiple project areas in a development environment
187 9,058,569 System and method for maintenance planning and failure prediction for equipment subject to periodic failure risk
188 9,058,568 System and method for maintenance planning and failure prediction for equipment subject to periodic failure risk
189 9,058,564 Controlling quarantining and biasing in cataclysms for optimization simulations
190 9,058,552 RFID tag temperature adaptation
191 9,058,505 Providing access control for public and private document fields
192 9,058,479 Pass-pattern authentication for computer-based security
193 9,058,473 User authentication via evoked potential in electroencephalographic signals
194 9,058,469 End user license agreement detection and monitoring
195 9,058,461 Transferring heat through an optical layer of integrated circuitry
196 9,058,460 Thermally-optimized metal fill for stacked chip systems
197 9,058,458 Structure for logic circuit and serializer-deserializer stack
198 9,058,457 Reticle data decomposition for focal plane determination in lithographic processes
199 9,058,456 Method and system to fix early mode slacks in a circuit design
200 9,058,455 Backside integration of RF filters for RF front end modules and design structure
201 9,058,448 Usage-based temporal degradation estimation for memory elements
202 9,058,444 Planning economic energy dispatch in electrical grid under uncertainty
203 9,058,443 Planning economic energy dispatch in electrical grid under uncertainty
204 9,058,441 Methods for modeling of FinFET width quantization
205 9,058,438 Application-requirement based configuration designer for distributed computing systems
206 9,058,430 Testing a software application interfacing with multiple external software applications in a simulated test environment
207 9,058,426 Identifying potential lock conditions in transactional software applications
208 9,058,417 Thread serialization and disablement tool
209 9,058,409 Contextual data visualization
210 9,058,383 Document processing method and system
211 9,058,374 Concept driven automatic section identification
212 9,058,370 Method, system and program product for defining imports into and exports out from a database system using spread sheets by use of a control language
213 9,058,359 Proactive risk analysis and governance of upgrade process
214 9,058,348 Method for building and maintaining trusted supplier records
215 9,058,344 Supporting flexible types in a database
216 9,058,339 Source control inheritance locking
217 9,058,338 Storing a small file with a reduced storage and memory footprint
218 9,058,319 Sub-model generation to improve classification accuracy
219 9,058,316 System and method for annotation of data visualizations
220 9,058,314 Dynamic editing of data representations using cascading weights
221 9,058,304 Continuous workload availability between sites at unlimited distances
222 9,058,302 Combined matrix-vector and matrix transpose vector multiply for a block-sparse matrix
223 9,058,301 Efficient transfer of matrices for matrix based operations
224 9,058,298 Integrated approach for deduplicating data in a distributed environment that involves a source and a target
225 9,058,293 Management of point-in-time copy relationship for extent space efficient volumes
226 9,058,291 Multiple erasure correcting codes for storage arrays
227 9,058,287 Relocating page tables and data amongst memory modules in a virtualized environment
228 9,058,276 Per-rank channel marking in a memory system
229 9,058,275 Data returned responsive to executing a start subchannel instruction
230 9,058,273 Frequency determination across an interface of a data processing system
231 9,058,270 False sharing detection logic for performance monitoring
232 9,058,265 Automated fault and recovery system
233 9,058,263 Automated fault and recovery system
234 9,058,260 Transient condition management utilizing a posted error detection processing protocol
235 9,058,250 In-situ computing system failure avoidance
236 9,058,245 Releasing blocks of storage class memory
237 9,058,244 Durable and coherent cache transactions between volatile and non-volatile memories
238 9,058,243 Releasing blocks of storage class memory
239 9,058,241 System and method for application configuration comparison and reuse
240 9,058,240 Multi-context remote development
241 9,058,239 Hypervisor subpartition as concurrent upgrade
242 9,058,235 Upgrade of software images based on streaming technique
243 9,058,231 Deployment of operating systems with detection of loop conditions
244 9,058,227 Transactional service pipeline
245 9,058,218 Resource allocation based on anticipated resource underutilization in a logically partitioned multi-processor environment
246 9,058,217 Preferential CPU utilization for tasks
247 9,058,195 Virtual machines failover
248 9,058,190 Comparing system engram with product engram to determine compatibility with system
249 9,058,178 Selective posted data error detection based on request type
250 9,058,174 Wiring web widgets of a web mashup
251 9,058,130 Tunable sector buffer for wide bandwidth resonant global clock distribution
252 9,058,121 Replicating tracks from a first storage site to a second and third storage sites
253 9,058,120 Setting optimal space allocation policy for creating dependent snapshots to enhance application write performance and reduce resource usage
254 9,058,114 Enabling throttling on average write throughput for solid state storage devices
255 9,058,112 Retrieving data in a storage system using thin provisioning
256 9,058,110 Managing a cache in a multi-node virtual tape controller
257 9,058,105 Automated adjustment of input configuration
258 9,058,080 User input device failure prediction
259 9,058,056 System and method of dynamically generating a frequency pattern to realize the sense of touch in a computing device
260 9,058,046 Leakage-aware voltage regulation circuit and method
261 9,058,034 Integrated circuit product yield optimization using the results of performance path testing
262 9,057,960 Resist performance for the negative tone develop organic development process
263 9,057,957 Extreme ultraviolet (EUV) radiation pellicle formation method
264 9,057,951 Chemically amplified photoresist composition and process for its use
265 9,057,915 Liquid crystal integrated circuit and method to fabricate same
266 9,057,861 Apparatus for cable organization
267 9,057,844 Grating edge coupler and method of forming same
268 9,057,832 Double layer interleaved p-n diode modulator
269 9,057,787 Colorimetric radiation dosimetry based on functional polymer and nanoparticle hybrid
270 9,057,766 Isolating failing latches using a logic built-in self-test
271 9,057,765 Scan compression ratio based on fault density
272 9,057,764 Detection of unchecked signals in circuit design verification
273 9,057,760 Circuit for detecting structural defects in an integrated circuit chip, methods of use and manufacture and design structures
274 9,057,741 Probe-on-substrate
275 9,057,719 Fluidic structure with nanopore array
276 9,057,693 Silicon oxide nanopore wetting and stabilization by molecular coating
277 9,057,670 Transmission electron microscope sample fabrication
278 9,057,539 Method of tracking and collecting solar energy
279 9,057,388 Vacuum trap
280 9,057,004 Slurry for chemical-mechanical polishing of metals and use thereof
281 9,056,592 Automobile airbag deployment dependent on passenger size
282 9,056,248 System and method for detecting inappropriate content in virtual worlds