IBM patents granted on 16 October 2007

92 US patents granted on 16 October 2007 and assigned to IBM

1 7,284,265 System and method for incremental refresh of a compiled access control table in a content management system
2 7,284,260 Method and apparatus for bit vector array
3 7,284,238 Multithread tracing method and apparatus
4 7,284,232 Automated generation of aliases based on embedded alias information
5 7,284,230 System for search and analysis of systematic defects in integrated circuits
6 7,284,210 Method for reconfiguration of random biases in a synthesized design without recompilation
7 7,284,204 System, method, and visual user interface for evaluating and selecting suppliers for enterprise procurement
8 7,284,198 Method and system for document draft reminder based on inactivity
9 7,284,195 Structure and method for linking within a website
10 7,284,184 Forward error correction scheme compatible with the bit error spreading of a scrambler
11 7,284,172 Access method for embedded JTAG TAP controller instruction registers
12 7,284,165 Computer generated documentation including diagram of computer system
13 7,284,158 Processor bus for performance monitoring with digests
14 7,284,156 Debugging a grid environment using ghost agents
15 7,284,153 Apparatus, method, and system for logging diagnostic information
16 7,284,150 System and method for reliably storing data and providing efficient incremental backup and asynchronous mirroring by preferentially handling new data
17 7,284,148 Method and system for self-healing in routers
18 7,284,147 Reliable fault resolution in a cluster
19 7,284,138 Deep power saving by disabling clock distribution without separate clock distribution for power management logic
20 7,284,112 Multiple page size address translation incorporating page size prediction
21 7,284,110 Configuration size determination in logically partitioned environment
22 7,284,105 Fast and economical establishment of remote copy
23 7,284,102 System and method of re-ordering store operations within a processor
24 7,284,100 Invalidating storage, clearing buffer entries, and an instruction therefor
25 7,284,097 Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes
26 7,284,095 Latency-aware replacement system and method for cache memories
27 7,284,094 Mechanism and apparatus allowing an N-way set associative cache, implementing a hybrid pseudo-LRU replacement algorithm, to have N L1 miss fetch requests simultaneously inflight regardless of their congruence class
28 7,284,093 Self-tuning cache
29 7,284,092 Digital data processing apparatus having multi-level register file
30 7,284,084 ROM scan memory expander
31 7,284,077 Peripheral interface system having dedicated communication channels
32 7,284,039 Apparatus and method for flexible web service deployment
33 7,284,034 Transparent combination of instant message protocols
34 7,284,029 4-to-2 carry save adder using limited switching dynamic logic
35 7,284,028 Comparator eliminating need for one’s complement logic for signed numbers
36 7,284,019 Apparatus, system, and method for differential backup using snapshot on-write data
37 7,284,012 Multiple attribute object comparison based on quantitative distance measurement
38 7,284,002 Calendar-enhanced awareness for instant messaging systems and electronic status boards
39 7,284,000 Automatic policy generation based on role entitlements and identity attributes
40 7,283,993 Methods, systems, and media for handling errors in script files
41 7,283,986 End-to-end business integration testing tool
42 7,283,982 Method and structure for transform regression
43 7,283,976 System and method for invoice imaging through negative confirmation process
44 7,283,970 Method and meeting scheduler for automated meeting insertion and rescheduling for busy calendars
45 7,283,953 Process for identifying excess noise in a computer system
46 7,283,949 System, method and program product for bidirectional text translation
47 7,283,947 Method and system for translation management of source language text phrases
48 7,283,687 Imaging for virtual cameras
49 7,283,644 System and method for enhancing security applications
50 7,283,562 Method and apparatus for scaling input bandwidth for bandwidth allocation technology
51 7,283,530 Apparatus and method to coordinate calendar searches in a network scheduler
52 7,283,529 Method and system for supporting a dedicated label switched path for a virtual private network over a label switched communication network
53 7,283,527 Apparatus and method of maintaining two-byte IP identification fields in IP headers
54 7,283,526 Method and system for providing a symmetric key for more efficient session identification
55 7,283,473 Apparatus, system and method for providing multiple logical channel adapters within a single physical channel adapter in a system area network
56 7,283,463 Non-disruptive reconfiguration of a publish/subscribe system
57 7,283,417 Write control circuitry and method for a memory array configured with multiple memory subarrays
58 7,283,411 Flood mode implementation for continuous bitline local evaluation circuit
59 7,283,410 Real-time adaptive SRAM array for high SEU immunity
60 7,283,404 Content addressable memory including a dual mode cycle boundary latch
61 7,283,359 Method and apparatus for acoustic noise reduction in a computer system having a vented cover
62 7,283,358 Apparatus and method for facilitating cooling of an electronics rack by mixing cooler air flow with re-circulating air flow in a re-circulation region
63 7,283,334 Method for fabricating seed layer for spin valve sensor for magnetic heads for hard disk drives
64 7,283,319 Ensuring rate of spin-up/spin-down cycles for spindle motor in a hard disk drive does not exceed rate spindle motor is designed to handle
65 7,283,093 Method and system for monitoring location based service emitter infrastructure
66 7,283,072 Methods of creating a dictionary for data compression
67 7,283,038 Comparing counter contents for timing critical applications
68 7,282,961 Apparatus for hysteresis based process compensation for CMOS receiver circuits
69 7,282,960 Dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock
70 7,282,949 FPGA powerup to known functional state
71 7,282,945 Wafer scale high density probe assembly, apparatus for use thereof and methods of fabrication thereof
72 7,282,943 Inspection device for inspecting TFT
73 7,282,942 Enhanced sampling methodology for semiconductor processing
74 7,282,899 Active impendance current-share method
75 7,282,802 Modified via bottom structure for reliability enhancement
76 7,282,799 Thermal interface with a patterned structure
77 7,282,790 Planar array contact memory cards
78 7,282,772 Low-capacitance contact for long gate-length devices with small contacted pitch
79 7,282,771 Structure and method for latchup suppression
80 7,282,710 Scanning probe microscopy tips composed of nanoparticles and methods to form same
81 7,282,458 Low K and ultra low K SiCOH dielectric films and methods to form the same
82 7,282,441 De-fluorination after via etch to preserve passivation
83 7,282,435 Method of forming contact for dual liner product
84 7,282,430 Melt-based patterning for electronic devices
85 7,282,425 Structure and method of integrating compound and elemental semiconductors for high-performance CMOS
86 7,282,423 Method of forming fet with T-shaped gate
87 7,282,404 Inexpensive method of fabricating a higher performance capacitance density MIMcap integrable into a copper interconnect scheme
88 7,282,403 Temperature stable metal nitride gate electrode
89 7,282,391 Method for precision assembly of integrated circuit chip packages
90 7,282,241 Patterned, high surface area substrate with hydrophilic/hydrophobic contrast, and method of use
91 7,282,148 Porous silicon composite structure as large filtration array
92 7,281,667 Method and structure for implementing secure multichip modules for encryption applications