Intel patents granted on 02 January 2007

45 US patents granted on 02 January 2007 and assigned to Intel

1 7,159,220 Flexible acceleration of java thread synchronization on multiprocessor computers
2 7,159,201 Method and apparatus for cut-point frontier selection and for counter-example generation in formal equivalence verification
3 7,159,169 Apparatus and methods for forward error correction decoding
4 7,159,154 Technique for synchronizing faults in a processor having a replay system
5 7,159,135 Method and apparatus for controlling a multi-mode I/O interface to enable an I/O buffer to transmit and receive data according to an I/O protocol
6 7,159,133 Low-power processor hint, such as from a pause instruction
7 7,159,109 Method and apparatus to manage address translation for secure connections
8 7,159,105 Platform-based optimization routines provided by firmware of a computer system
9 7,159,091 Dynamic relocation of execute in place applications
10 7,159,077 Direct processor cache access within a system having a coherent multi-processor protocol
11 7,159,066 Precharge suggestion
12 7,159,060 PCI standard hot-plug controller (SHPC) with user programmable command execution timing
13 7,159,051 Free packet buffer allocation
14 7,159,046 Method and apparatus for configuring communication between devices in a computer system
15 7,159,030 Associating a packet with a flow
16 7,159,010 Network abstraction of input/output devices
17 7,158,964 Queue management
18 7,158,911 Methods and apparatus for thermal management of an integrated circuit die
19 7,158,813 Antenna for wireless systems
20 7,158,778 Method for virtual network connectivity for powered off stations in wireless LAN networks
21 7,158,632 Adaptive scaling and echo reduction
22 7,158,631 Efficient echo cancellation techniques
23 7,158,594 Receivers for controlled frequency signals
24 7,158,532 Half duplex link with isochronous and asynchronous arbitration
25 7,158,517 Method and apparatus for frame-based protocol processing
26 7,158,438 Network packet buffer allocation optimization in memory bank systems
27 7,158,381 Heat sink assembly and method of attaching a heat sink to an electronic device on a motherboard
28 7,158,275 Polarization modulator
29 7,158,178 Method of converting a sub-sampled color image
30 7,158,147 Method and apparatus for pixel filtering using shared filter resource between overlay and texture mapping engines
31 7,158,111 Flexible display
32 7,157,950 Method and apparatus to construct a fifty percent (50%) duty cycle clock signal across power domains
33 7,157,947 Power supplies noise detector for integrated circuits
34 7,157,924 Method and apparatus for on-die voltage fluctuation detection
35 7,157,894 Low power start-up circuit for current mirror based reference generators
36 7,157,787 Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices
37 7,157,755 Polymer sacrificial light absorbing structure and method
38 7,157,380 Damascene process for fabricating interconnect layers in an integrated circuit
39 7,157,379 Strained semiconductor structures
40 7,157,378 Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
41 7,157,301 Semiconductor package security features using thermochromatic inks and three-dimensional identification coding
42 7,157,230 Electron induced fluorescent method for nucleic acid sequencing
43 7,156,947 Energy enhanced surface planarization
44 7,155,819 System for making a conductive circuit on a substantially non-conductive substrate
45 D534,545 Media device