36 US patents granted on 02 March 2010 and assigned to Intel
| 1 | 7,673,345 | Providing extended memory protection |
| 2 | 7,673,254 | Apparatus, system and method for context and language specific data entry |
| 3 | 7,673,170 | Personal computer bus protocol with error correction mode |
| 4 | 7,673,129 | Secure booting from a memory device |
| 5 | 7,673,128 | Methods and apparatus to facilitate fast restarts in processor systems |
| 6 | 7,673,126 | Methods and apparatus to self-initialize a processor |
| 7 | 7,673,113 | Method for dynamic load balancing on partitioned systems |
| 8 | 7,673,111 | Memory system with both single and consolidated commands |
| 9 | 7,673,090 | Hot plug interface control method and apparatus |
| 10 | 7,673,073 | Multiphase encoded protocol and synchronization of buses |
| 11 | 7,673,041 | Method to perform exact string match in the data plane of a network processor |
| 12 | 7,673,026 | Speed sensitive content delivery in a client-server network |
| 13 | 7,672,657 | Tunable filter apparatus, systems, and methods |
| 14 | 7,672,653 | Removing interfering signals in a broadband radio frequency receiver |
| 15 | 7,672,529 | Techniques to detect Gaussian noise |
| 16 | 7,672,407 | Mitigation of interference from periodic noise |
| 17 | 7,672,387 | Multiple input, multiple output wireless communication system, associated methods and data structures |
| 18 | 7,672,372 | Method and system for data management in a video decoder |
| 19 | 7,672,365 | Apparatus and methods for communicating using symbol-modulated subcarriers |
| 20 | 7,672,335 | Non-integer word size translation through rotation of different buffer alignment channels |
| 21 | 7,672,178 | Dynamic adaptive read return of DRAM data |
| 22 | 7,672,132 | Electronic packaging apparatus and method |
| 23 | 7,672,120 | Interchangeable keyboard for computer systems |
| 24 | 7,671,865 | Refresh of display |
| 25 | 7,671,694 | Programmable passive equalizer |
| 26 | 7,671,471 | Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode |
| 27 | 7,671,456 | Power management integrated circuit |
| 28 | 7,671,414 | Semiconductor on insulator apparatus |
| 29 | 7,671,358 | Plasma implantated impurities in junction region recesses |
| 30 | 7,671,120 | Chain extension for thermal materials |
| 31 | 7,670,951 | Grid array connection device and method |
| 32 | 7,670,928 | Ultra-thin oxide bonding for S1 to S1 dual orientation bonding |
| 33 | 7,670,919 | Integrated capacitors in package-level structures, processes of making same, and systems containing same |
| 34 | 7,670,894 | Selective high-k dielectric film deposition for semiconductor device |
| 35 | 7,670,866 | Multi-die molded substrate integrated circuit device |
| 36 | 7,670,167 | Socket that engages a pin grid array |
