62 US patents granted on 05 January 2016 and assigned to Intel
| 1 | D746,821 | Electronic device with retractable leg support |
| 2 | 9,232,686 | Thin film based electromagnetic interference shielding with BBUL/coreless packages |
| 3 | 9,232,639 | Non-uniform substrate stackup |
| 4 | 9,232,536 | Maintenance of channel usage in a wireless communication system |
| 5 | 9,232,503 | Apparatus and method for cell information indication in a wireless network |
| 6 | 9,232,498 | Techniques for traffic delivery to a group of devices |
| 7 | 9,232,437 | Evolved node B, user equipment, and method for operation of narrow bandwidth user equipment in wide bandwidth broadband networks |
| 8 | 9,232,436 | Single MPDU frame signaling |
| 9 | 9,232,203 | Image processing device, imaging device, image processing method, imaging method, and image processing program for pseudo-color supression in an image |
| 10 | 9,232,177 | Video chat data processing |
| 11 | 9,232,154 | Object selection in an image |
| 12 | 9,232,149 | Determining a final exposure setting automatically for a solid state camera without a separate light metering circuit |
| 13 | 9,232,041 | System and method for sending local information from a wireless browser to a web server |
| 14 | 9,231,864 | Techniques for packet management in an input/output virtualization system |
| 15 | 9,231,814 | Communication device, method for generating a transport protocol message, and method for processing a transport protocol message |
| 16 | 9,231,809 | Methods and arrangements for phase tracking in wireless networks |
| 17 | 9,231,760 | Wireless device and method for rekeying with reduced packet loss for high-throughput wireless communications |
| 18 | 9,231,753 | Low power oversampling with reduced-architecture delay locked loop |
| 19 | 9,231,740 | Transmitter noise in system budget |
| 20 | 9,231,723 | Coordinated dynamic point selection (DPS) with cell range expansion in a coordinated multipoint (CoMP) system |
| 21 | 9,231,714 | Methods for calibrating a transmitter, and radio transmitter |
| 22 | 9,231,681 | Apparatus, system and method of wireless backhaul and access communication via a common antenna array |
| 23 | 9,231,675 | Receiver and method for detecting a pre-coded signal |
| 24 | 9,231,602 | A-priori-probability-phase-estimation for digital phase-locked loops |
| 25 | 9,231,561 | Multi-stage adaptive filter |
| 26 | 9,231,524 | Digital transceiver with switched capacitor sampling mixers and switched capacitor amplifiers |
| 27 | 9,231,519 | Temperature compensation for oscillator |
| 28 | 9,231,434 | Charging a battery using a multi-rate charge |
| 29 | 9,231,331 | Connector identification through proximity sensing |
| 30 | 9,231,318 | Integrated package insertion and loading mechanism (iPILM) |
| 31 | 9,231,204 | Low voltage embedded memory having conductive oxide and electrode stacks |
| 32 | 9,231,202 | Thermal-disturb mitigation in dual-deck cross-point memories |
| 33 | 9,231,194 | High stability spintronic memory |
| 34 | 9,231,076 | Enhanced dislocation stress transistor |
| 35 | 9,230,944 | Techniques and configurations associated with a capductor assembly |
| 36 | 9,230,900 | Ground via clustering for crosstalk mitigation |
| 37 | 9,230,877 | Methods of forming serpentine thermal interface material and structures formed thereby |
| 38 | 9,230,833 | Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures |
| 39 | 9,230,636 | Apparatus for dual purpose charge pump |
| 40 | 9,230,614 | Separate microchannel voltage domains in stacked memory architecture |
| 41 | 9,230,297 | Systems, methods, and computer program products for compound image demosaicing and warping |
| 42 | 9,230,139 | Selective content sharing on computing devices |
| 43 | 9,230,120 | Architecture and instruction set for implementing advanced encryption standard (AES) |
| 44 | 9,230,116 | Technique for providing secure firmware |
| 45 | 9,230,081 | User authorization and presence detection in isolation from interference from and control by host central processing unit and operating system |
| 46 | 9,230,032 | Poll-based networking system |
| 47 | 9,229,897 | Embedded control channel for high speed serial interconnect |
| 48 | 9,229,895 | Multi-core integrated circuit configurable to provide multiple logical domains |
| 49 | 9,229,879 | Power reduction using unmodified information in evicted cache lines |
| 50 | 9,229,874 | Apparatus and method for compressing a memory address |
| 51 | 9,229,872 | Semiconductor chip with adaptive BIST cache testing during runtime |
| 52 | 9,229,853 | Method and system for data de-duplication |
| 53 | 9,229,836 | Coexisting standard and proprietary connection usage |
| 54 | 9,229,828 | Mechanism for achieving high memory reliability, availability and serviceability |
| 55 | 9,229,761 | Generating, at least in part, at least one packet indicating, at least in part, at least one command and/or issuing, at least in part, at least one result of execution, at least in part, of the at least one command |
| 56 | 9,229,720 | Circuit marginality validation test for an integrated circuit |
| 57 | 9,229,719 | Method and apparatus for shuffling data |
| 58 | 9,229,718 | Method and apparatus for shuffling data |
| 59 | 9,229,524 | Performing local power gating in a processor |
| 60 | 9,229,517 | Computer input device power savings |
| 61 | 9,229,466 | Fully integrated voltage regulators for multi-stack integrated circuit architectures |
| 62 | 9,229,054 | Self-contained, path-level aging monitor apparatus and method |
