Intel patents granted on 09 June 2015

49 US patents granted on 09 June 2015 and assigned to Intel

1 9,055,594 Reducing transmission signal artifact spacing
2 9,055,533 Wireless communication device and method for improved WiFi and bluetooth coexistence usingreduced power for control packets
3 9,055,523 Apparatus, system and method of calibrating a radio delay of a wireless device
4 9,055,477 Handling wait time in a congested wireless communication network
5 9,055,474 Apparatus for improved mobility in a wireless heterogeneous network
6 9,055,315 System and method for providing integrated media
7 9,055,177 Content aware video resizing
8 9,055,011 Methods and apparatus for linked-list circular buffer management
9 9,054,987 Single instruction processing of network packets
10 9,054,938 Quadrature gain and phase imbalance correction
11 9,054,933 Orthogonal frequency division multiplex (OFDM) receiver with phase noise mitigation and reduced latency
12 9,054,925 Parallel digital-to-time converter architecture
13 9,054,921 Method and apparatus for generating a plurality of modulated signals
14 9,054,908 RFI mitigation using burst timing
15 9,054,902 Apparatus and system for switching equalization
16 9,054,858 Transmission and detection in multiple-antenna transmission systems
17 9,054,855 Synchronizing phases between local LO generation circuits
18 9,054,769 Pre-processing unit for a signal processor
19 9,054,742 Error and erasure decoding apparatus and method
20 9,054,720 System, apparatus and method to improve analog-to-digital converter output
21 9,054,642 Systems and methods to provide compensated feedback phase information
22 9,054,302 Perpendicular spin transfer torque memory (STTM) device with enhanced stability and method to form same
23 9,054,215 Patterning of vertical nanowire transistor channel and gate with directed self assembly
24 9,054,190 Methods of containing defects for non-silicon device engineering
25 9,054,178 Self-aligned contacts
26 9,054,164 Method of forming high density, high shorting margin, and low capacitance interconnects by alternating recessed trenches
27 9,054,068 Etchstop layers and capacitors
28 9,053,812 Fast exit from DRAM self-refresh
29 9,053,550 Techniques for rapid stereo reconstruction from images
30 9,053,523 Joint enhancement of lightness, color and contrast of images and video
31 9,053,354 Fast face detection technique
32 9,053,346 Low-overhead cryptographic method and apparatus for providing memory confidentiality, integrity and replay protection
33 9,053,308 Multi electro-biometric user recognition
34 9,053,267 Noise analysis using timing models
35 9,053,251 Providing a sideband message interface for system on a chip (SoC)
36 9,053,244 Utilization-aware low-overhead link-width modulation for power reduction in interconnects
37 9,053,059 Roots-of-trust for measurement of virtual machines
38 9,053,042 Method, system, and device for modifying a secure enclave configuration without changing the enclave measurement
39 9,053,040 Filtering mechanism for render target line modification
40 9,053,025 Apparatus and method for fast failure handling of instructions
41 9,053,022 Synchronous software interface for an accelerated compute engine
42 9,053,014 Repurposing NAND ready/busy pin as completion interrupt
43 9,052,985 Method and apparatus for efficient programmable cyclic redundancy check (CRC)
44 9,052,947 Unified optimistic and pessimistic concurrency control for a software transactional memory (STM) system
45 9,052,902 Techniques to transmit commands to a target device to reduce power consumption
46 9,052,901 Method, apparatus, and system for energy efficiency and energy conservation including configurable maximum processor current
47 9,052,899 Idle power reduction for memory subsystems
48 9,052,893 Various methods and apparatuses for power states in a controller
49 9,052,890 Execute at commit state update instructions, apparatus, methods, and systems