42 US patents granted on 12 May 2009 and assigned to Intel
| 1 | 7,533,374 | Adaptively storing system code in non-volatile storage |
| 2 | 7,533,316 | Method and apparatus for disabling and swapping cores in a multi-core microprocessor |
| 3 | 7,533,300 | Configurable error handling apparatus and methods to operate the same |
| 4 | 7,533,286 | Regulating application of clock to control current rush (DI/DT) |
| 5 | 7,533,252 | Overriding a static prediction with a level-two predictor |
| 6 | 7,533,247 | Operation frame filtering, building, and execution |
| 7 | 7,533,234 | Method and apparatus for storing compressed code without an index table |
| 8 | 7,533,232 | Accessing data from different memory locations in the same cycle |
| 9 | 7,533,215 | Distributed and packed metadata structure for disk cache |
| 10 | 7,533,204 | Enumeration of devices on a memory channel |
| 11 | 7,533,201 | Queue management mechanism in network processor wherein packets stored at memory device corresponds to addresses stored in plurity of queues within queue management |
| 12 | 7,533,191 | Methods and arrangements for devices to share a common address on a bus |
| 13 | 7,533,190 | Network storage target boot and network connectivity through a common network device |
| 14 | 7,533,186 | Integrated security framework |
| 15 | 7,533,014 | Method and system for concurrent use of two or more closely coupled communication recognition modalities |
| 16 | 7,532,793 | Segmented waveguide coupler |
| 17 | 7,532,789 | Process tolerant planar ring resonator dispersion compensator |
| 18 | 7,532,765 | Run length encoded digital image |
| 19 | 7,532,732 | Method and apparatus for VoIP telephony call announcement |
| 20 | 7,532,675 | Techniques to time vary pilot locations in wireless networks |
| 21 | 7,532,636 | High bus bandwidth transfer using split data bus |
| 22 | 7,532,611 | Controlling wireless communications between linked devices |
| 23 | 7,532,564 | Sub-banded ultra-wideband communications systems |
| 24 | 7,532,528 | Sense amplifier method and arrangement |
| 25 | 7,532,515 | Voltage reference generator using big flash cell |
| 26 | 7,532,509 | Segmented bit line for flash memory |
| 27 | 7,532,498 | Memory device, circuits and methods for reading a memory device |
| 28 | 7,532,476 | Flow solutions for microelectronic cooling |
| 29 | 7,532,083 | Active nonlinear transmission line |
| 30 | 7,532,070 | Analog variable gain amplifier with improved dynamic range characteristics |
| 31 | 7,532,023 | Apparatus and methods for self-heating burn-in processes |
| 32 | 7,531,879 | Method and resultant structure for floating body memory on bulk wafer |
| 33 | 7,531,836 | Body bias compensation for aged transistors |
| 34 | 7,531,726 | Controlled alignment of nanobarcodes encoding specific information for scanning probe microscopy (SPM) reading |
| 35 | 7,531,437 | Method of forming metal gate electrodes using sacrificial gate electrode material and sacrificial gate dielectric material |
| 36 | 7,531,429 | Methods and apparatuses for manufacturing ultra thin device layers for integrated circuit devices |
| 37 | 7,531,404 | Semiconductor device having a metal gate electrode formed on an annealed high-k gate dielectric layer |
| 38 | 7,531,393 | Non-planar MOS structure with a strained channel region |
| 39 | 7,531,295 | Method and apparatus for lithographic imaging using asymmetric illumination |
| 40 | 7,531,102 | Simultaneous selective polymer deposition and etch pitch doubling for sub 50nm line/space patterning |
| 41 | 7,530,814 | Providing variable sized contacts for coupling with a semiconductor device |
| 42 | 7,530,164 | Wafer-level underfill process making use of sacrificial contact pad protective material |
