38 US patents granted on 15 April 2008 and assigned to Intel
| 1 | 7,360,220 | Methods and apparatus for multi-threading using differently coded software segments to perform an algorithm |
| 2 | 7,360,103 | P-state feedback to operating system with hardware coordination |
| 3 | 7,360,033 | Hierarchical virtual model of a cache hierarchy in a multiprocessor system |
| 4 | 7,360,031 | Method and apparatus to enable I/O agents to perform atomic operations in shared, coherent memory spaces |
| 5 | 7,360,027 | Method and apparatus for initiating CPU data prefetches by an external agent |
| 6 | 7,360,022 | Synchronizing an instruction cache and a data cache on demand |
| 7 | 7,360,015 | Preventing storage of streaming accesses in a cache |
| 8 | 7,360,008 | Enforcing global ordering through a caching bridge in a multicore multiprocessor system |
| 9 | 7,360,007 | System including a segmentable, shared bus |
| 10 | 7,359,949 | Remotely controlling a UNIX-based system |
| 11 | 7,359,727 | Systems and methods for adjusting transmit power in wireless local area networks |
| 12 | 7,359,619 | Transmitting signals to cause replays to be recorded at a plurality of receivers |
| 13 | 7,359,608 | Constructing well structures for hybrid optical waveguides |
| 14 | 7,359,591 | Electrical/optical integration scheme using direct copper bonding |
| 15 | 7,359,532 | Fingerprint minutiae matching using scoring techniques |
| 16 | 7,359,518 | Distribution of secured information |
| 17 | 7,359,464 | Trellis decoder and method of decoding |
| 18 | 7,359,364 | Monitoring in communication system with wireless trunk |
| 19 | 7,359,231 | Providing current for phase change memories |
| 20 | 7,359,211 | Local control of underfill flow on high density packages, packages and systems made therewith, and methods of making same |
| 21 | 7,359,210 | Shock absorbing system for circuit boards |
| 22 | 7,358,825 | Variable capacitance circuit arrangement |
| 23 | 7,358,824 | Variable capacitance circuit arrangement |
| 24 | 7,358,770 | Driver circuit |
| 25 | 7,358,615 | Microelectronic package having multiple conductive paths through an opening in a support substrate |
| 26 | 7,358,607 | Substrates and systems to minimize signal path discontinuities |
| 27 | 7,358,606 | Apparatus to compensate for stress between heat spreader and thermal interface material |
| 28 | 7,358,597 | UV-activated dielectric layer |
| 29 | 7,358,580 | Sacrificial layer technique to make gaps in MEMS applications |
| 30 | 7,358,579 | Reducing the actuation voltage of microelectromechanical system switches |
| 31 | 7,358,547 | Selective deposition to improve selectivity and structures formed thereby |
| 32 | 7,358,521 | Lateral phase change memory and method therefor |
| 33 | 7,358,444 | Folded substrate with interposer package for integrated circuit devices |
| 34 | 7,358,201 | Methods of forming channels on an integrated circuit die and die cooling systems including such channels |
| 35 | 7,358,121 | Tri-gate devices and methods of fabrication |
| 36 | 7,358,116 | Substrate conductive post formation |
| 37 | 7,358,111 | Imageable bottom anti-reflective coating for high resolution lithography |
| 38 | 7,357,293 | Soldering an electronics package to a motherboard |
