Intel patents granted on 25 November 2014

27 US patents granted on 25 November 2014 and assigned to Intel

1 RE45,262 Voice-controlled navigation device utilizing wireless data transmission for obtaining maps and real-time overlay information
2 D718,300 Multiple mode display device
3 8,898,749 Method and system for generating one-time passwords
4 8,898,646 Method and apparatus for flexible, accurate, and/or efficient code profiling
5 8,898,532 Multi-carier configuration, activation and scheduling
6 8,898,499 Platform and processor power management
7 8,898,494 Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
8 8,898,393 Optimized ring protocols and techniques
9 8,898,390 Scheduling workloads based on cache asymmetry
10 8,897,831 Wireless device content information theft protection system
11 8,897,712 Device, system and method of wireless communication via multiple antenna assemblies
12 8,897,702 Mobility measurement using CSI-RS in additional carrier
13 8,897,701 Efficient method to overcome frequency errors within four time slots
14 8,897,412 Method and apparatus for phase noise mitigation
15 8,897,351 Method for peak to average power ratio reduction
16 8,897,268 Apparatus and method adapted for directional bandwidth reservation with fixed announcement slot in wireless networks
17 8,897,216 Method and apparatus for supporting AMD re-segmentation
18 8,897,185 Device, system and method of scheduling communications with a group of wireless communication units
19 8,897,054 ROM device with keepers
20 8,897,047 Associative memory oscillator array
21 8,896,560 Offloading touch processing to a graphics processor
22 8,896,116 Microelectronic package and method of manufacturing same
23 8,896,110 Paste thermal interface materials
24 8,896,101 Nonplanar III-N transistors with compositionally graded semiconductor channels
25 8,896,066 Tin doped III-V material contacts
26 8,896,030 Integrated circuits with selective gate electrode recess
27 8,895,365 Techniques and configurations for surface treatment of an integrated circuit substrate