36 US patent applications published on 12 January 2006 and assigned to Micron
| 1 | 20060009136 | Fixed-abrasive chemical-mechanical planarization of titanium nitride |
| 2 | 20060009035 | Method for forming polysilicon local interconnects |
| 3 | 20060008989 | Method for forming an array with polysilicon local interconnects |
| 4 | 20060008988 | Method of forming a memory cell |
| 5 | 20060008987 | Method for forming a floating gate memory with polysilicon local interconnects |
| 6 | 20060008978 | Decoupling capacitor for high frequency noise immunity |
| 7 | 20060008966 | Memory utilizing oxide-conductor nanolaminates |
| 8 | 20060008963 | Method for forming polysilicon local interconnects |
| 9 | 20060008946 | Castellation wafer level packaging of integrated circuit chips |
| 10 | 20060008926 | Semiconductor fabrication that includes surface tension control |
| 11 | 20060008758 | System for two-step resist soft bake to prevent ILD outgassing during semiconductor processing |
| 12 | 20060008741 | Transparent amorphous carbon structure in semiconductor devices |
| 13 | 20060007764 | Semiconductor fabrication that includes surface tension control |
| 14 | 20060007760 | Programmable DQS preamble |
| 15 | 20060007759 | Alignment of memory read data and clocking |
| 16 | 20060007750 | Flash memory |
| 17 | 20060007749 | Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices |
| 18 | 20060007748 | Methods for neutralizing holes in tunnel oxides in tunnel oxides of floating-gate memory cells and devices |
| 19 | 20060007747 | Flash memory |
| 20 | 20060007746 | Methods for neutralizing holes in tunnel oxides of floating-gate memory cells and devices |
| 21 | 20060007744 | Flash memory |
| 22 | 20060007743 | Flash memory |
| 23 | 20060007633 | Decoupling capacitor for high frequency noise immunity |
| 24 | 20060007616 | Power supply voltage detection circuitry and methods for use of the same |
| 25 | 20060006553 | Electronic device package |
| 26 | 20060006548 | H2 plasma treatment |
| 27 | 20060006519 | Castellation wafer level packaging of integrated circuit chips |
| 28 | 20060006499 | Controlling diffusion in doped semiconductor regions |
| 29 | 20060006497 | Capacitors having doped aluminum oxide dielectrics |
| 30 | 20060006456 | Memory cells and select gates of NAND memory arrays |
| 31 | 20060006455 | Memory cell with polysilicon local interconnects |
| 32 | 20060006451 | Use of selective epitaxial silicon growth in formation of floating gates |
| 33 | 20060006448 | Localized masking for semiconductor structure development |
| 34 | 20060006445 | Container capacitor structure and method of formation thereof |
| 35 | 20060006444 | Selective epitaxy vertical integrated circuit components and methods |
| 36 | 20060006442 | Process for making a silicon-on-insulator ledge and structures achieved thereby |
