24 US patent applications published on 14 August 2014 and assigned to Micron
| 1 | 20140229926 | UNROLLING QUANTIFICATIONS TO CONTROL IN-DEGREE AND/OR OUT-DEGREE OF AUTOMATON |
| 2 | 20140229925 | METHOD AND APPARATUS FOR COMPILING REGULAR EXPRESSIONS |
| 3 | 20140229777 | AUTORECOVERY AFTER MANUFACTURING/SYSTEM INTEGRATION |
| 4 | 20140229762 | FAILURE RECOVERY MEMORY DEVICES AND METHODS |
| 5 | 20140229745 | SYSTEM AND METHOD FOR UPDATING READ-ONLY MEMORY IN SMART CARD MEMORY MODULES |
| 6 | 20140229702 | CONCURRENT MEMORY OPERATIONS |
| 7 | 20140229687 | METHOD AND APPARATUS FOR CALIBRATING A MEMORY INTERFACE WITH A NUMBER OF DATA PATTERNS |
| 8 | 20140229660 | LOGICAL ADDRESS OFFSET |
| 9 | 20140227863 | METHODS OF FORMING A METAL TELLURIDE MATERIAL, RELATED METHODS OF FORMING A SEMICONDUCTOR DEVICE STRUCTURE, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES |
| 10 | 20140227852 | Capacitor Forming Methods |
| 11 | 20140227842 | 3D STRUCTURED MEMORY DEVICES AND METHODS FOR MANUFACTURING THEREOF |
| 12 | 20140227674 | SYSTEM AND METHOD FOR MANAGING CONTINUED ATTENTION TO DISTANCE-LEARNING CONTENT |
| 13 | 20140226427 | MEMORY DEVICE WORD LINE DRIVERS AND METHODS |
| 14 | 20140226425 | CURRENT MODE SENSE AMPLIFIER WITH PASSIVE LOAD |
| 15 | 20140226392 | Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells and Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells |
| 16 | 20140225656 | OUTPUT SLEW RATE CONTROL |
| 17 | 20140225282 | SYSTEM IN PACKAGE (SIP) WITH DUAL LAMINATE INTERPOSERS |
| 18 | 20140225264 | METHOD FOR PROVIDING ELECTRICAL CONNECTIONS TO SPACED CONDUCTIVE LINES |
| 19 | 20140225259 | SEMICONDUCTOR MODULE SYSTEM HAVING ENCAPSULATED THROUGH WIRE INTERCONNECT (TWI) |
| 20 | 20140225254 | METHOD AND APPARATUS PROVIDING INTEGRATED CIRCUIT HAVING REDISTRIBUTION LAYER WITH RECESSED CONNECTORS |
| 21 | 20140225175 | Semiconductor Constructions, DRAM Arrays, and Methods of Forming Semiconductor Constructions |
| 22 | 20140225171 | TECHNIQUES FOR FORMING A CONTACT TO A BURIED DIFFUSION LAYER IN A SEMICONDUCTOR MEMORY DEVICE |
| 23 | 20140225028 | WET ETCHANTS INCLUDING AT LEAST ONE ETCH BLOCKER |
| 24 | 20140224646 | SILVER SELENIDE FILM STOICHIOMETRY AND MORPHOLOGY CONTROL IN SPUTTER DEPOSITION |
