30 US patents granted on 02 December 2008 and assigned to Micron
| 1 | D581,926 | Storage device |
| 2 | 7,461,320 | Memory system and method having selective ECC during low power refresh |
| 3 | 7,461,306 | Output data compression scheme using tri-state |
| 4 | 7,461,286 | System and method for using a learning sequence to establish communications on a high-speed nonsynchronous interface in the absence of clock forwarding |
| 5 | 7,461,188 | Capacitive multidrop bus compensation |
| 6 | 7,461,139 | Network computer providing mass storage, broadband access, and other enhanced functionality |
| 7 | 7,460,432 | Sequential access memory with system and method |
| 8 | 7,460,430 | Memory devices having reduced coupling noise between wordlines |
| 9 | 7,460,429 | Circuit and method for reducing power in a memory device during standby modes |
| 10 | 7,460,398 | Programming a memory with varying bits per cell |
| 11 | 7,459,944 | Low current wide VREF range input buffer |
| 12 | 7,459,930 | Digital calibration circuits, devices and systems including same, and methods of operation |
| 13 | 7,459,923 | Probe interposers and methods of fabricating probe interposers |
| 14 | 7,459,797 | Standoffs for centralizing internals in packaging process |
| 15 | 7,459,778 | Chip on board leadframe for semiconductor components having area array |
| 16 | 7,459,773 | Stackable ball grid array |
| 17 | 7,459,764 | Method of manufacture of a PCRAM memory cell |
| 18 | 7,459,757 | Transistor structures |
| 19 | 7,459,746 | Method of forming inside rough and outside smooth HSG electrodes and capacitor structure |
| 20 | 7,459,742 | Method of manufacturing sidewall spacers on a memory device, and device comprising same |
| 21 | 7,459,740 | Integrated DRAM-NVRAM multi-level memory |
| 22 | 7,459,739 | Double density MRAM with planar processing |
| 23 | 7,459,668 | Method, apparatus, and system to reduce ground resistance in a pixel array |
| 24 | 7,459,638 | Absorbing boundary for a multi-layer circuit board structure |
| 25 | 7,459,393 | Method for fabricating semiconductor components with thinned substrate, circuit side contacts, conductive vias and backside contacts |
| 26 | 7,459,363 | Line edge roughness reduction |
| 27 | 7,459,362 | Methods of forming DRAM arrays |
| 28 | 7,459,346 | Intrinsic thermal enhancement for FBGA package |
| 29 | 7,459,336 | Method of forming a chalcogenide material containing device |
| 30 | 7,458,466 | Stack processing tray for integrated circuit devices |
