Micron patents granted on 03 October 2006

70 US patents granted on 03 October 2006 and assigned to Micron

1 7,117,402 Background block erase check for flash memories
2 7,117,316 Memory hub and access method having internal row caching
3 7,117,299 DRAM with hidden refresh
4 7,116,841 Apparatus, method, and product for downscaling an image
5 7,116,602 Method and system for controlling refresh to avoid memory cell data losses
6 7,116,600 Memory device having terminals for transferring multiple types of data
7 7,116,596 Method of apparatus for enhanced sensing of low voltage memory
8 7,116,590 Memory address repair without enable fuses
9 7,116,589 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
10 7,116,588 Low supply voltage temperature compensated reference voltage generator and method
11 7,116,584 Multiple erase block tagging in a flash memory device
12 7,116,570 Access circuit and method for allowing external test voltage to be applied to isolated wells
13 7,116,368 CMOS APS pixel sensor dynamic range increase
14 7,116,366 CMOS aps pixel sensor dynamic range increase
15 7,116,143 Synchronous clock generator including duty cycle correction
16 7,116,133 Apparatus and method for adjusting clock skew
17 7,116,129 Temperature-compensated output buffer method and circuit
18 7,116,124 Apparatus to prevent damage to probe card
19 7,116,122 Method for ball grid array chip packages having improved testing and stacking characteristics
20 7,116,118 Method and apparatus for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
21 7,116,042 Flow-fill structures
22 7,116,001 Bumped die and wire bonded board-on-chip package
23 7,116,000 Underfilled, encapsulated semiconductor die assemblies and methods of fabrication
24 7,115,998 Multi-component integrated circuit contacts
25 7,115,992 Electrode structure for use in an integrated circuit
26 7,115,990 Bumped die and wire bonded board-on-chip package
27 7,115,986 Flexible ball grid array chip scale packages
28 7,115,984 Semiconductor devices including peripherally located bond pads, intermediates thereof, assemblies, and packages including the semiconductor devices, and support elements for the semiconductor devices
29 7,115,982 Semiconductor component having stiffener, stacked dice and circuit decals
30 7,115,981 Semiconductor device assemblies including interposers with dams protruding therefrom
31 7,115,976 Method and apparatus for epoxy LOC die attachment
32 7,115,970 Capacitor for use in an integrated circuit
33 7,115,961 Packaged microelectronic imaging devices and methods of packaging microelectronic imaging devices
34 7,115,957 Semiconductor raised source-drain structure
35 7,115,948 Transistor constructions and electronic devices
36 7,115,939 Floating gate transistor with horizontal gate layers stacked next to vertical body
37 7,115,932 Semiconductor device incorporating an electrical contact to an internal conductive layer and method for making the same
38 7,115,929 Semiconductor constructions comprising aluminum oxide and metal oxide dielectric materials
39 7,115,928 Dual-damascene bit line structures for microelectronic devices and methods of fabricating microelectronic devices
40 7,115,926 Capacitor constructions, DRAM constructions, and semiconductive material assemblies
41 7,115,923 Imaging with gate controlled charge storage
42 7,115,855 Image sensor having pinned floating diffusion diode
43 7,115,853 Micro-lens configuration for small lens focusing in digital imaging devices
44 7,115,819 Positioning flowable solder for bonding integrated circuit elements
45 7,115,532 Methods of forming patterned photoresist layers over semiconductor substrates
46 7,115,529 Atomic layer deposition methods
47 7,115,528 Systems and method for forming silicon oxide layers
48 7,115,527 Methods of etching an aluminum oxide comprising substrate, and methods of forming a capacitor
49 7,115,525 Method for integrated circuit fabrication using pitch multiplication
50 7,115,524 Methods of processing a semiconductor substrate
51 7,115,515 Methods for forming capacitor structures
52 7,115,512 Methods of forming semiconductor constructions
53 7,115,509 Method for forming polysilicon local interconnects
54 7,115,506 Method of making a contact structure
55 7,115,504 Method of forming electrode structure for use in an integrated circuit
56 7,115,495 Methods of making projected contact structures for engaging bumped semiconductor devices
57 7,115,493 Antifuse structures, methods, and applications
58 7,115,492 Technique for elimination of pitting on silicon substrate during gate stack etch using material in a non-annealed state
59 7,115,489 Methods of growing epitaxial silicon
60 7,115,480 Micromechanical strained semiconductor by wafer bonding
61 7,115,458 Gate coupling in floating-gate memory cells
62 7,115,451 Methods of forming semiconductor circuitry
63 7,115,422 Separation apparatus including porous silicon column
64 7,115,166 Systems and methods for forming strontium- and/or barium-containing layers
65 7,115,016 Apparatus and method for mechanical and/or chemical-mechanical planarization of micro-device workpieces
66 7,114,976 Test socket and test system for semiconductor components with easily removable nest
67 7,114,669 Methods of operating a liquid vaporizer
68 7,114,532 Liner for use in processing chamber
69 7,114,404 System and method for detecting flow in a mass flow controller
70 7,114,248 Method of handling an electrical component