22 US patents granted on 08 April 2008 and assigned to Micron
| 1 | 7,356,723 | Method and apparatus for data transfer |
| 2 | 7,355,922 | Method and apparatus for initialization of read latency tracking circuit in high-speed DRAM |
| 3 | 7,355,920 | Write latency tracking using a delay lock loop in a synchronous DRAM |
| 4 | 7,355,894 | Programming flash memories |
| 5 | 7,355,464 | Apparatus and method for controlling a delay- or phase-locked loop as a function of loop frequency |
| 6 | 7,355,423 | Method for optimizing probe card design |
| 7 | 7,355,387 | System and method for testing integrated circuit timing margins |
| 8 | 7,355,273 | Semiconductor dice having back side redistribution layer accessed using through-silicon vias, methods |
| 9 | 7,355,267 | Substrate, semiconductor die, multichip module, and system including a via structure comprising a plurality of conductive elements |
| 10 | 7,355,244 | Electrical devices with multi-walled recesses |
| 11 | 7,355,232 | Memory devices with dual-sided capacitors |
| 12 | 7,355,231 | Memory circuitry with oxygen diffusion barrier layer received over a well base |
| 13 | 7,355,229 | Masked spacer etching for imagers |
| 14 | 7,355,222 | Imaging device having a pixel cell with a transparent conductive interconnect line and the method of making the pixel cell |
| 15 | 7,355,203 | Use of gate electrode workfunction to improve DRAM refresh |
| 16 | 7,354,863 | Methods of selectively removing silicon |
| 17 | 7,354,842 | Methods of forming conductive materials |
| 18 | 7,354,812 | Multiple-depth STI trenches in integrated circuit fabrication |
| 19 | 7,354,795 | Methods for packaging and encapsulating semiconductor device assemblies that include tape substrates |
| 20 | 7,354,793 | Method of forming a PCRAM device incorporating a resistance-variable chalocogenide element |
| 21 | 7,354,631 | Chemical vapor deposition apparatus and methods |
| 22 | 7,354,329 | Method of forming a monolithic base plate for a field emission display (FED) device |
