24 US patents granted on 10 January 2006 and assigned to Micron
1 | 6,986,084 | Apparatus and method for reducing test resources in testing DRAMS |
2 | 6,985,847 | System and method for process matching |
3 | 6,985,393 | Device for margin testing a semiconductor memory by applying a stressing voltage simultaneously to complementary and true digit lines |
4 | 6,985,391 | High speed redundant data sensing method and apparatus |
5 | 6,985,382 | Bridge-type magnetic random access memory (MRAM) latch |
6 | 6,985,375 | Adjusting the frequency of an oscillator for use in a resistive sense amp |
7 | 6,985,235 | Cascaded fiber fabry-perot filters |
8 | 6,984,894 | Semiconductor package having a partial slot cover for encapsulation process |
9 | 6,984,893 | Low temperature nitride used as Cu barrier layer |
10 | 6,984,891 | Methods for making copper and other metal interconnections in integrated circuits |
11 | 6,984,886 | System-on-a-chip with multi-layered metallized through-hole interconnection |
12 | 6,984,874 | Semiconductor device with metal fill by treatment of mobility layers including forming a refractory metal nitride using TMEDT |
13 | 6,984,854 | Edge intensive antifuse |
14 | 6,984,592 | Systems and methods for forming metal-doped alumina |
15 | 6,984,583 | Stereolithographic method for forming insulative coatings for via holes in semiconductor devices |
16 | 6,984,570 | Wafer bonding method of forming silicon-on-insulator comprising integrated circuitry |
17 | 6,984,549 | Methods of forming semiconductor fuse arrangements |
18 | 6,984,547 | Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation |
19 | 6,984,545 | Methods of encapsulating selected locations of a semiconductor die assembly using a thick solder mask |
20 | 6,984,544 | Die to die connection method and assemblies and packages including dice so connected |
21 | 6,984,537 | Method of forming two-transistor pixel with buried reset channel |
22 | 6,984,301 | Methods of forming capacitor constructions |
23 | 6,983,551 | Interconnecting substrates for electrical coupling of microelectronic components |
24 | 6,983,536 | Method and apparatus for manufacturing known good semiconductor die |