Micron patents granted on 11 September 2007

46 US patents granted on 11 September 2007 and assigned to Micron

1 7,269,765 Method and apparatus for storing failing part locations in a module
2 7,269,686 Synchronous memory open page register
3 7,269,685 Apparatus and methods for storing data in a magnetic random access memory (MRAM)
4 7,269,094 Memory system and method for strobing data, command and address signals
5 7,269,091 Word line driver circuitry and methods for using the same
6 7,269,083 Using redundant memory for extra features
7 7,269,079 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
8 7,269,072 NROM memory cell, memory array, related devices and methods
9 7,269,071 NROM memory cell, memory array, related devices and methods
10 7,269,066 Programming memory devices
11 7,269,044 Method and apparatus for accessing a memory array
12 7,269,042 Memory stacking system and method
13 7,269,040 Static content addressable memory cell
14 7,268,949 Microlens array sheet and manufacturing method thereof
15 7,268,869 In-situ spectrograph and method of measuring light wavelength characteristics for photolithography
16 7,268,614 Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of generating a bias reference
17 7,268,603 Method and apparatus for reducing duty cycle distortion of an output signal
18 7,268,574 Systems and methods for sensing obstructions associated with electrical testing of microfeature workpieces
19 7,268,531 Apparatus for improving stability and lock time for synchronous circuits
20 7,268,482 Preventing junction leakage in field emission devices
21 7,268,481 Field emission display with smooth aluminum film
22 7,268,413 Bipolar transistors with low-resistance emitter contacts
23 7,268,402 Memory cell with trench-isolated transistor including first and second isolation trenches
24 7,268,388 One-transistor composite-gate memory
25 7,268,384 Semiconductor substrate having first and second pairs of word lines
26 7,268,382 DRAM cells
27 7,268,078 Chemical vapor deposition of titanium from titanium tetrachloride and hydrocarbon reactants
28 7,268,072 Method and structure for reducing contact aspect ratios
29 7,268,067 Semiconductor integrated circuit package having electrically disconnected solder balls for mounting
30 7,268,059 Methods for securing components of semiconductor device assemblies to each other with adhesive materials that include pressure-sensitive and curable components
31 7,268,057 Methods of filling openings with oxide, and methods of forming trenched isolation regions
32 7,268,054 Methods for increasing photo-alignment margins
33 7,268,039 Method of forming a contact using a sacrificial structure
34 7,268,035 Methods of forming semiconductor constructions comprising cerium oxide and titanium oxide
35 7,268,034 Methods of forming pluralities of capacitors, and integrated circuitry
36 7,268,031 Memory device with high dielectric constant gate dielectrics and metal floating gates
37 7,268,030 Methods of forming semiconductor constructions
38 7,268,023 Method of forming a pseudo SOI substrate and semiconductor devices
39 7,268,022 Stable PD-SOI devices and methods
40 7,268,018 Method for fabricating semiconductor component with stiffener and circuit decal
41 7,268,013 Method of fabricating a semiconductor die package having improved inductance characteristics
42 7,268,012 Methods for fabrication of thin semiconductor assemblies including redistribution layers and packages and assemblies formed thereby
43 7,268,004 Thermoelectric control for field emission display
44 7,267,999 MRAM layer having domain wall traps
45 7,267,608 Method and apparatus for conditioning a chemical-mechanical polishing pad
46 7,266,879 Method for magnetically establishing an electrical connection with a contact of a semiconductor device component