34 US patents granted on 12 August 2014 and assigned to Micron
| 1 | 8,806,316 | Circuits, integrated circuits, and methods for interleaved parity computation |
| 2 | 8,806,303 | Apparatuses, systems, devices, and methods of replacing at least partially non-functional portions of memory |
| 3 | 8,806,293 | Controller to execute error correcting code algorithms and manage NAND memories |
| 4 | 8,806,263 | Methods and apparatuses including a global timing generator and local control circuits |
| 5 | 8,806,164 | Apparatus, electronic devices and methods associated with an operative transition from a first interface to a second interface |
| 6 | 8,806,155 | Methods and apparatus for designating or using data status indicators |
| 7 | 8,806,152 | Method and apparatus for sending data from multiple sources over a communications bus |
| 8 | 8,806,131 | Multi-serial interface stacked-die memory architecture |
| 9 | 8,806,090 | Apparatus including buffer allocation management and related methods |
| 10 | 8,804,452 | Data interleaving module |
| 11 | 8,804,451 | Power source and power source control circuit |
| 12 | 8,804,449 | Apparatus and methods to provide power management for memory devices |
| 13 | 8,804,432 | Sensing for all bit line architecture in a memory device |
| 14 | 8,804,428 | Determining system lifetime characteristics |
| 15 | 8,804,424 | Memory with three transistor memory cell device |
| 16 | 8,804,419 | Memory kink checking |
| 17 | 8,804,416 | Memory devices having select gates with p type bodies, memory strings having separate source lines and methods |
| 18 | 8,804,414 | Spin torque transfer memory cell structures and methods |
| 19 | 8,804,411 | Dual mode clock and data scheme for memory programming |
| 20 | 8,804,399 | Multi-function resistance change memory cells and apparatuses including the same |
| 21 | 8,803,307 | Stacked microelectronic devices and methods for manufacturing stacked microelectronic devices |
| 22 | 8,803,240 | Electronic device with asymmetric gate strain |
| 23 | 8,803,229 | Nanowire transistor with surrounding gate |
| 24 | 8,803,228 | Memory arrays with rows of memory cells coupled to opposite sides of a control gate |
| 25 | 8,803,214 | Three dimensional memory and methods of forming the same |
| 26 | 8,803,213 | Floating body memory cell apparatus and methods |
| 27 | 8,803,125 | Cross-point memory utilizing Ru/Si diode |
| 28 | 8,803,118 | Semiconductor constructions and memory arrays |
| 29 | 8,802,573 | Methods of etching trenches into silicon of a semiconductor substrate, methods of forming trench isolation in silicon of a semiconductor substrate, and methods of forming a plurality of diodes |
| 30 | 8,802,526 | Methods of forming reverse mode non-volatile memory cell structures |
| 31 | 8,802,525 | Methods of forming charge storage structures including etching diffused regions to form recesses |
| 32 | 8,802,520 | Method of forming a field effect transistor having source/drain material over insulative material |
| 33 | 8,802,461 | Vertical light emitting devices with nickel silicide bonding and methods of manufacturing |
| 34 | 8,801,894 | Sub-10 NM line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers |
