22 US patents granted on 16 February 2010 and assigned to Micron
| 1 | 7,664,999 | Real time testing using on die termination (ODT) circuit |
| 2 | 7,664,216 | Digital frequency locked delay line |
| 3 | 7,663,952 | Capacitor supported precharging of memory digit lines |
| 4 | 7,663,934 | Program method with optimized voltage level for flash memory |
| 5 | 7,663,930 | Programming a non-volatile memory device |
| 6 | 7,663,926 | Cell deterioration warning apparatus and method |
| 7 | 7,663,925 | Method and apparatus for programming flash memory |
| 8 | 7,663,901 | Techniques for implementing accurate device parameters stored in a database |
| 9 | 7,663,232 | Elongated fasteners for securing together electronic components and substrates, semiconductor device assemblies including such fasteners, and accompanying systems |
| 10 | 7,663,224 | Semiconductor BGA package having a segmented voltage plane |
| 11 | 7,663,206 | Interposer including at least one passive element at least partially defined by a recess formed therein, system including same, and wafer-scale interposer |
| 12 | 7,663,137 | Phase change memory cell and method of formation |
| 13 | 7,663,133 | Memory elements having patterned electrodes and method of forming the same |
| 14 | 7,662,729 | Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer |
| 15 | 7,662,719 | Slurry for use in polishing semiconductor device conductive structures that include copper and tungsten and polishing methods |
| 16 | 7,662,718 | Trim process for critical dimension control for integrated circuits |
| 17 | 7,662,701 | Gettering of silicon on insulator using relaxed silicon germanium epitaxial proximity layers |
| 18 | 7,662,693 | Lanthanide dielectric with controlled interfaces |
| 19 | 7,662,658 | Photodiode with ultra-shallow junction for high quantum efficiency CMOS image sensor and method of formation |
| 20 | 7,662,649 | Methods for assessing alignments of substrates within deposition apparatuses; and methods for assessing thicknesses of deposited layers within deposition apparatuses |
| 21 | 7,662,648 | Integrated circuit inspection system |
| 22 | 7,662,299 | Nanoimprint lithography template techniques for use during the fabrication of a semiconductor device and systems including same |
