21 US patents granted on 16 February 2016 and assigned to Micron
| 1 | 9,264,068 | Deflate compression algorithm |
| 2 | 9,264,050 | Apparatuses and methods for delaying signals using a delay line with homogenous architecture and integrated measure initialization circuitry |
| 3 | 9,263,675 | Switching components and memory units |
| 4 | 9,263,674 | ETCH bias homogenization |
| 5 | 9,263,672 | Transistors, memory cells and semiconductor constructions |
| 6 | 9,263,577 | Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors |
| 7 | 9,263,461 | Apparatuses including memory arrays with source contacts adjacent edges of sources |
| 8 | 9,263,460 | Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate |
| 9 | 9,263,455 | Methods of forming an array of conductive lines and methods of forming an array of recessed access gate lines |
| 10 | 9,263,341 | Methods of forming transistors |
| 11 | 9,263,133 | Techniques for providing a semiconductor memory device |
| 12 | 9,263,130 | Memory device page buffer configuration and methods |
| 13 | 9,263,128 | Methods and apparatuses for programming memory cells |
| 14 | 9,263,115 | Semiconductor device |
| 15 | 9,263,111 | Sub-block disabling in 3D memory |
| 16 | 9,263,104 | Semiconductor device |
| 17 | 9,263,095 | Memory having buried digit lines and methods of making the same |
| 18 | 9,262,335 | Re-building mapping information for memory devices |
| 19 | 9,262,317 | Non-volatile configuration for serial non-volatile memory |
| 20 | 9,262,261 | Memory devices facilitating differing depths of error detection and/or error correction coverage |
| 21 | 9,259,683 | Methods and apparatus for treating fluorinated greenhouse gases in gas streams |
