22 US patents granted on 16 June 2009 and assigned to Micron
| 1 | 7,549,143 | Method and device for checking lithography data |
| 2 | 7,549,142 | Method and device for checking lithography data |
| 3 | 7,549,033 | Dual edge command |
| 4 | 7,549,011 | Bit inversion in memory devices |
| 5 | 7,548,667 | Optical integrated circuit |
| 6 | 7,548,483 | Memory device and method having multiple address, data and command buses |
| 7 | 7,548,459 | Method, apparatus, and system providing adjustable memory page configuration |
| 8 | 7,547,978 | Underfill and encapsulation of semiconductor assemblies with materials having differing properties |
| 9 | 7,547,954 | Electronic systems using optical waveguide interconnects formed through a semiconductor wafer |
| 10 | 7,547,949 | Semiconductor structures and memory device constructions |
| 11 | 7,547,945 | Transistor devices, transistor structures and semiconductor constructions |
| 12 | 7,547,935 | Semiconductor devices including buried digit lines that are laterally offset from corresponding active-device regions |
| 13 | 7,547,905 | Programmable conductor memory cell structure and method therefor |
| 14 | 7,547,877 | Microelectronic imagers with integrated optical devices and methods for manufacturing such microelectronic imagers |
| 15 | 7,547,850 | Semiconductor device assemblies with compliant spring contact structures |
| 16 | 7,547,640 | Method for integrated circuit fabrication using pitch multiplication |
| 17 | 7,547,617 | Semiconductor device including container having epitaxial silicon therein |
| 18 | 7,547,604 | Method of forming a recessed gate structure on a substrate having insulating columns and removing said insulating columns after forming a conductive region of the gate structure |
| 19 | 7,547,599 | Multi-state memory cell |
| 20 | 7,547,579 | Underfill process |
| 21 | 7,547,559 | Method for forming MRAM bit having a bottom sense layer utilizing electroless plating |
| 22 | 7,547,213 | Memory modules and methods for manufacturing memory modules |
