Micron patents granted on 16 October 2007

42 US patents granted on 16 October 2007 and assigned to Micron

1 7,284,169 System and method for testing write strobe timing margins in memory devices
2 7,283,663 Interpolation of edge portions of a digital image
3 7,283,418 Memory device and method having multiple address, data and command buses
4 7,283,394 Trench corner effect bidirectional flash memory cell
5 7,283,205 Optimized optical lithography illumination source for use during the manufacture of a semiconductor device
6 7,283,164 Method for detecting and correcting defective pixels in a digital image sensor
7 7,283,080 High density row RAM for column parallel CMOS image sensors
8 7,283,035 Radio frequency data communications device with selectively removable antenna portion and method
9 7,282,996 Electronic amplifier with signal gain dependent bias
10 7,282,972 Bias generator with feedback control
11 7,282,948 MOS linear region impedance curvature correction
12 7,282,947 Memory module and method having improved signal routing topology
13 7,282,939 Circuit having a long device configured for testing
14 7,282,932 Compliant contact pin assembly, card system and methods thereof
15 7,282,806 Semiconductor devices at least partially covered by a composite coating including particles dispersed through photopolymer material
16 7,282,805 Bond pad rerouting element and stacked semiconductor device assemblies including the rerouting element
17 7,282,793 Multiple die stack apparatus employing T-shaped interposer elements
18 7,282,792 Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
19 7,282,789 Back-to-back semiconductor device assemblies
20 7,282,784 Methods of manufacture of a via structure comprising a plurality of conductive elements and methods of forming multichip modules including such via structures
21 7,282,783 Resistance variable memory device and method of fabrication
22 7,282,762 4F.sup.2 EEPROM NROM memory arrays with vertical devices
23 7,282,756 Structurally-stabilized capacitors and method of making of same
24 7,282,685 Multi-point correlated sampling for image sensors
25 7,282,666 Method and apparatus to increase throughput of processing using pulsed radiation sources
26 7,282,457 Apparatus for stabilizing high pressure oxidation of a semiconductor device
27 7,282,447 Method for an integrated circuit contact
28 7,282,443 Methods of forming metal silicide
29 7,282,440 Integrated circuit contact
30 7,282,439 Anti-reflective coating doped with carbon for use in integrated circuit technology and method of formation
31 7,282,433 Interconnect structures with bond-pads and methods of forming bump sites on bond-pads
32 7,282,409 Isolation structure for a memory cell using Al.sub.2O.sub.3 dielectric
33 7,282,408 Surface treatment of an oxide layer to enhance adhesion of a ruthenium metal layer
34 7,282,401 Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
35 7,282,400 Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction
36 7,282,397 Methods for designing bond pad rerouting elements for use in stacked semiconductor device assemblies and for assembling semiconductor devices
37 7,282,392 Method of fabricating a stacked die in die BGA package
38 7,282,390 Stacked die-in-die BGA package with die having a recess
39 7,282,387 Electro- and electroless plating of metal in the manufacture of PCRAM devices
40 7,282,239 Systems and methods for depositing material onto microfeature workpieces in reaction chambers
41 7,282,131 Methods of electrochemically treating semiconductor substrates
42 7,281,952 Edge connector including internal layer contact, printed circuit board and electronic module incorporating same