Micron patents granted on 18 September 2007

64 US patents granted on 18 September 2007 and assigned to Micron

1 7,272,758 Defective memory block identification in a memory device
2 7,272,747 Use of non-volatile memory to perform rollback function
3 7,272,742 Method and apparatus for improving output skew for synchronous integrated circuits
4 7,272,709 Using chip select to specify boot memory
5 7,272,703 Program controlled embedded-DRAM-DSP architecture and methods
6 7,272,697 Systems and methods for managing data stored in a multi-drive storage device
7 7,272,696 Dynamic volume management
8 7,272,694 Chip protection register lock circuit in a flash memory device
9 7,272,683 Memory device controller
10 7,272,682 Memory hub bypass circuit and method
11 7,272,678 DSP bus monitoring apparatus and method
12 7,272,066 Method and system for controlling refresh to avoid memory cell data losses
13 7,272,054 Time domain bridging circuitry for use in determining output enable timing
14 7,272,046 High voltage switching circuit
15 7,272,045 Method for programming and erasing an NROM cell
16 7,272,044 Flash memory
17 7,272,039 Minimizing adjacent wordline disturb in a memory device
18 7,271,654 Low voltage CMOS differential amplifier
19 7,271,635 Method and apparatus for reducing duty cycle distortion of an output signal
20 7,271,628 Reduced current input buffer circuit
21 7,271,620 Variable impedance output buffer
22 7,271,611 Method for testing semiconductor components using bonded electrical connections
23 7,271,581 Integrated circuit characterization printed circuit board, test equipment including same, method of fabrication thereof and method of characterizing an integrated circuit device
24 7,271,528 Uniform emitter array for display devices
25 7,271,491 Carrier for wafer-scale package and wafer-scale package including the carrier
26 7,271,482 Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods
27 7,271,467 Multiple oxide thicknesses for merged memory and logic applications
28 7,271,464 Liner for shallow trench isolation
29 7,271,463 Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base
30 7,271,445 Ultra-thin semiconductors bonded on glass substrates
31 7,271,440 Method and apparatus for forming an integrated circuit electrode having a reduced contact area
32 7,271,438 Self-aligned silicide for word lines and contacts
33 7,271,437 Non-volatile memory with hole trapping barrier
34 7,271,435 Modified source/drain re-oxidation method and system
35 7,271,433 High-density single transistor vertical memory gain cell
36 7,271,413 Semiconductor constructions
37 7,271,407 Switchable circuit assemblies and semiconductor constructions
38 7,271,106 Critical dimension control for integrated circuits
39 7,271,096 Method for improved deposition of dielectric material
40 7,271,092 Boron incorporated diffusion barrier material
41 7,271,089 Barrier layer, IC via, and IC line forming methods
42 7,271,086 Microfeature workpieces and methods of forming a redistribution layer on microfeature workpieces
43 7,271,085 Method of fabricating a semiconductor interconnect structure
44 7,271,077 Deposition methods with time spaced and time abutting precursor pulses
45 7,271,072 Stud electrode and process for making same
46 7,271,071 Method of forming a catalytic surface comprising at least one of Pt, Pd, Co and Au in at least one of elemental and alloy forms
47 7,271,065 Horizontal memory devices with vertical gates
48 7,271,064 Method of forming a field effect transistor using conductive masking material
49 7,271,060 Semiconductor processing methods
50 7,271,057 Memory array with overlapping buried digit line and active area and method for forming same
51 7,271,053 Methods of forming capacitors and electronic devices
52 7,271,052 Long retention time single transistor vertical memory gain cell
53 7,271,051 Methods of forming a plurality of capacitor devices
54 7,271,050 Silicon nanocrystal capacitor and process for forming same
55 7,271,037 Leadframe alteration to direct compound flow into package
56 7,271,036 Leadframe alteration to direct compound flow into package
57 7,271,027 Castellation wafer level packaging of integrated circuit chips
58 7,271,025 Image sensor with SOI substrate
59 7,271,018 Method of forming a support frame for semiconductor packages
60 7,271,016 Methods and apparatus for a flexible circuit interposer
61 7,270,917 Prevention of photoresist scumming
62 7,270,715 Chemical vapor deposition apparatus
63 7,270,596 Chemical mechanical polishing process
64 7,269,898 Method for making an edge intensive antifuse