34 US patents granted on 19 February 2008 and assigned to Micron
| 1 | 7,333,908 | Techniques for generating test patterns in high speed memory devices |
| 2 | 7,333,674 | Suppression of ringing artifacts during image resizing |
| 3 | 7,333,520 | Apparatus for multiplexing signals through I/O pins |
| 4 | 7,333,384 | Techniques for storing accurate operating current values |
| 5 | 7,333,370 | Method to prevent bit line capacitive coupling |
| 6 | 7,333,366 | Common wordline flash array architecture |
| 7 | 7,333,355 | Techniques for implementing accurate operating current values stored in a database |
| 8 | 7,333,267 | Micro-lenses for CMOS imagers |
| 9 | 7,333,145 | Camera module |
| 10 | 7,332,950 | DLL measure initialization circuit for high frequency operation |
| 11 | 7,332,946 | Power supply voltage detection circuitry and methods for use of the same |
| 12 | 7,332,820 | Stacked die in die BGA package |
| 13 | 7,332,819 | Stacked die in die BGA package |
| 14 | 7,332,811 | Integrated circuit interconnect |
| 15 | 7,332,790 | Semiconductor device having an active area partially isolated by a lateral cavity |
| 16 | 7,332,789 | Isolation trenches for memory devices |
| 17 | 7,332,786 | Anti-blooming storage pixel |
| 18 | 7,332,773 | Vertical device 4F.sup.2 EEPROM memory |
| 19 | 7,332,767 | High density memory devices having improved channel widths and cell size |
| 20 | 7,332,759 | Method and structure to reduce optical crosstalk in a solid state imager |
| 21 | 7,332,737 | Isolation trench geometry for image sensors |
| 22 | 7,332,735 | Phase change memory cell and method of formation |
| 23 | 7,332,703 | Imaging structure including a pixel with multiple signal readout circuits and methods of operation for imaging structure |
| 24 | 7,332,442 | Systems and methods for forming metal oxide layers |
| 25 | 7,332,419 | Structure and method of fabricating a transistor having a trench gate |
| 26 | 7,332,418 | High-density single transistor vertical memory gain cell |
| 27 | 7,332,413 | Semiconductor wafers including one or more reinforcement structures and methods of forming the same |
| 28 | 7,332,408 | Isolation trenches for memory devices |
| 29 | 7,332,401 | Method of fabricating an electrode structure for use in an integrated circuit |
| 30 | 7,332,389 | Selective polysilicon stud growth |
| 31 | 7,332,388 | Method to simultaneously form both fully silicided and partially silicided dual work function transistor gates during the manufacture of a semiconductor device, semiconductor devices, and systems including same |
| 32 | 7,332,376 | Method of encapsulating packaged microelectronic devices with a barrier |
| 33 | 7,332,372 | Methods for forming assemblies and packages that include stacked semiconductor devices separated a distance defined by adhesive material interposed therebetween |
| 34 | 7,332,032 | Precursor mixtures for use in preparing layers on substrates |
