21 US patents granted on 23 June 2009 and assigned to Micron
| 1 | RE40,790 | Method for making electrical contact with an active area through sub-micron contact openings and a semiconductor device |
| 2 | 7,552,364 | Diagnostic and managing distributed processor system |
| 3 | 7,552,274 | Flash memory architecture with separate storage of overhead and user data |
| 4 | 7,551,510 | Memory block reallocation in a flash memory device |
| 5 | 7,551,509 | Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory |
| 6 | 7,551,481 | User configurable commands for flash memory |
| 7 | 7,551,467 | Memory device architectures and operation |
| 8 | 7,551,466 | Bit line coupling |
| 9 | 7,550,985 | Methods of testing memory devices |
| 10 | 7,550,848 | Semiconductor constructions comprising particle-containing materials |
| 11 | 7,550,847 | Packaged microelectronic devices and methods for packaging microelectronic devices |
| 12 | 7,550,824 | Low k interconnect dielectric using surface transformation |
| 13 | 7,550,818 | Method of manufacture of a PCRAM memory cell |
| 14 | 7,550,816 | Filled trench isolation structure |
| 15 | 7,550,762 | Isolation circuit |
| 16 | 7,550,380 | Electroless plating of metal caps for chalcogenide-based memory devices |
| 17 | 7,550,345 | Methods of forming hafnium-containing materials |
| 18 | 7,550,341 | High density stepped, non-planar flash memory |
| 19 | 7,550,340 | Silicon rich barrier layers for integrated circuit devices |
| 20 | 7,550,339 | Memory device with high dielectric constant gate dielectrics and metal floating gates |
| 21 | 7,550,315 | Method for fabricating semiconductor package with multi-layer die contact and external contact |
