Micron patents granted on 25 September 2007

59 US patents granted on 25 September 2007 and assigned to Micron

1 7,275,190 Memory block quality identification in a memory device
2 7,275,172 Apparatus and method for generating a delayed clock signal
3 7,275,130 Method and system for dynamically operating memory in a power-saving error correcting mode
4 7,274,838 Method for fabricating an optical integrated circuit
5 7,274,611 Method and architecture to calibrate read operations in synchronous flash memory
6 7,274,609 High speed redundant data sensing method and apparatus
7 7,274,607 Bitline exclusion in verification operation
8 7,274,606 Low power chip select (CS) latency option
9 7,274,605 Per-bit set-up and hold time adjustment for double-data rate synchronous DRAM
10 7,274,604 Memory device having terminals for transferring multiple types of data
11 7,274,600 NAND flash memory with read and verification threshold uniformity
12 7,274,596 Reduction of adjacent floating gate data pattern sensitivity
13 7,274,591 Write current shunting compensation
14 7,274,582 High speed data bus
15 7,274,397 Image sensor with active reset and randomly addressable pixels
16 7,274,396 Image sensors with isolated flushed pixel reset
17 7,274,319 Ramp generators for imager analog-to-digital converters
18 7,274,239 Method and apparatus to set a tuning range for an analog delay
19 7,274,237 Measure control delay and method having latching circuit integral with delay circuit
20 7,274,236 Variable delay line with multiple hierarchy
21 7,274,228 Method and apparatus for digital phase generation at high frequencies
22 7,274,221 Comparator circuit
23 7,274,220 Method and apparatus for amplifying a regulated differential signal to a higher voltage
24 7,274,205 System and method for testing devices utilizing capacitively coupled signaling
25 7,274,204 System and method for testing devices utilizing capacitively coupled signaling
26 7,274,201 Method and system for stressing semiconductor wafers during burn-in
27 7,274,197 Contact system for interfacing a semiconductor wafer to an electrical tester
28 7,274,138 Spacers for field emission displays
29 7,274,095 Interposers with receptacles for receiving semiconductor devices and assemblies and packages including such interposers
30 7,274,094 Leadless packaging for image sensor devices
31 7,274,086 Memory device power distribution in memory assemblies
32 7,274,076 Threshold voltage adjustment for long channel transistors
33 7,274,068 Ballistic direct injection NROM cell on strained silicon structures
34 7,274,067 Service programmable logic arrays with low tunnel barrier interpoly insulators
35 7,274,065 Source lines for NAND memory devices
36 7,274,061 Capacitor constructions
37 7,274,059 Capacitor constructions
38 7,274,056 Semiconductor constructions
39 7,274,054 Dual capacitor structure for imagers and method of formation
40 7,274,049 Semiconductor assemblies
41 7,274,034 Resistance variable memory device with sputtered metal-chalcogenide region and method of fabrication
42 7,273,817 Conditioning of a reaction chamber
43 7,273,816 Methods for removal of organic materials
44 7,273,809 Method of fabricating a conductive path in a semiconductor device
45 7,273,802 Methods for consolidating previously unconsolidated conductive material to form conductive structures or contact pads or secure conductive structures to contact pads
46 7,273,797 Methods of forming semiconductor-on-insulator constructions
47 7,273,796 Methods of forming trench isolation in the fabrication of integrated circuitry and methods of fabricating integrated circuitry
48 7,273,793 Methods of filling gaps using high density plasma chemical vapor deposition
49 7,273,791 Methods for forming a conductive structure using oxygen diffusion through one metal layer to oxidize a second metal layer
50 7,273,788 Ultra-thin semiconductors bonded on glass substrates
51 7,273,784 Scalable high density non-volatile memory cells in a contactless memory array
52 7,273,779 Method of forming a double-sided capacitor
53 7,273,778 Method of electroplating a substance over a semiconductor substrate
54 7,273,769 Method and apparatus for removing encapsulating material from a packaged microelectronic device
55 7,273,684 Mask having transmissive elements and a common sidelobe inhibitor for sidelobe suppression in radiated patterning
56 7,273,660 Mixed composition interface layer and method of forming
57 7,273,566 Gas compositions
58 7,273,525 Methods for forming phosphorus- and/or boron-containing silica layers on substrates
59 7,273,411 Polishing apparatus