25 US patents granted on 26 November 2013 and assigned to Micron
| 1 | 8,595,655 | Method and system for lithographic simulation and verification |
| 2 | 8,595,542 | Explicit skew interface for reducing crosstalk and simultaneous switching noise |
| 3 | 8,595,537 | DLL phase detection using advanced phase equalization |
| 4 | 8,595,447 | Communication between internal and external processors |
| 5 | 8,595,424 | Cluster based non-volatile memory translation layer |
| 6 | 8,595,423 | Method of storing data on a flash memory device |
| 7 | 8,595,422 | Memory devices and methods of storing data on a memory device |
| 8 | 8,595,415 | At least semi-autonomous modules in a memory system and methods |
| 9 | 8,593,889 | Asynchronous/synchronous interface |
| 10 | 8,593,876 | Sensing scheme in a memory device |
| 11 | 8,593,873 | Apparatuses and methods of reprogramming memory cells |
| 12 | 8,593,869 | Apparatuses and methods including memory array and data line architecture |
| 13 | 8,593,849 | Memory device interface methods, apparatus, and systems |
| 14 | 8,593,187 | Delay line off-state control with power reduction |
| 15 | 8,593,175 | Boolean logic in a state machine lattice |
| 16 | 8,593,001 | Patterned semiconductor bases |
| 17 | 8,592,985 | Methods of forming conductive structures and methods of forming DRAM cells |
| 18 | 8,592,964 | Apparatus and method for high density multi-chip structures |
| 19 | 8,592,940 | Topography based patterning |
| 20 | 8,592,898 | Vertical gated access transistor |
| 21 | 8,592,897 | Semiconductor device comprising transistor structures and methods for forming same |
| 22 | 8,592,797 | Variable resistance memory device having reduced bottom contact area and method of forming the same |
| 23 | 8,592,795 | Multilevel mixed valence oxide (MVO) memory |
| 24 | 8,592,254 | Microelectronic devices with improved heat dissipation and methods for cooling microelectronic devices |
| 25 | 8,590,146 | Connection verification technique |
