28 US patents granted on 28 February 2006 and assigned to Micron
| 1 | 7,007,255 | Integrated circuit design using charge pump modeling |
| 2 | 7,007,133 | Synchronous memory open page register |
| 3 | 7,006,746 | Waveguide for thermo optic device |
| 4 | 7,006,394 | Apparatus and method for semiconductor device repair with reduced number of programmable elements |
| 5 | 7,006,393 | Method and apparatus for semiconductor device repair with reduced number of programmable elements |
| 6 | 7,006,392 | Memory redundancy programming |
| 7 | 7,006,389 | Voltage translator for multiple voltage operations |
| 8 | 7,006,382 | Programming flash memories |
| 9 | 7,006,227 | Apparatus for the in situ alignment of a mask and a semiconductor wafer |
| 10 | 7,006,075 | Ergonomic computer mouse |
| 11 | 7,005,966 | Remote computer controller and control method |
| 12 | 7,005,961 | Secure cargo transportation system |
| 13 | 7,005,878 | Method for in-line testing of flip-chip semiconductor assemblies |
| 14 | 7,005,870 | Interconnect bump plate |
| 15 | 7,005,754 | Method of ball grid array (BGA) alignment, method of testing, alignment apparatus and semiconductor device assembly |
| 16 | 7,005,731 | Plastic lead frames for semiconductor devices and packages including same |
| 17 | 7,005,710 | Transistors having controlled conductive spacers, uses of such transistors and methods of making such transistors |
| 18 | 7,005,697 | Method of forming a non-volatile electron storage memory and the resulting device |
| 19 | 7,005,695 | Integrated circuitry including a capacitor with an amorphous and a crystalline high K capacitor dielectric region |
| 20 | 7,005,692 | Memory cell arrays |
| 21 | 7,005,628 | Amplifier with variable signal gain and matched gain bandwidth |
| 22 | 7,005,379 | Semiconductor processing methods for forming electrical contacts |
| 23 | 7,005,344 | Method of forming a device with a gallium nitride or gallium aluminum nitride gate |
| 24 | 7,005,342 | Method to fabricate surface p-channel CMOS |
| 25 | 7,005,316 | Method for package reduction in stacked chip and board assemblies |
| 26 | 7,004,817 | Carrier assemblies, planarizing apparatuses including carrier assemblies, and methods for planarizing micro-device workpieces |
| 27 | 7,004,054 | In-process tape bur monitoring |
| 28 | 7,003,874 | Methods of bonding solder balls to bond pads on a substrate |
