Micron patents granted on 29 April 2008

37 US patents granted on 29 April 2008 and assigned to Micron

1 7,366,985 Text based markup language resource interface
2 7,366,966 System and method for varying test signal durations and assert times for testing memory devices
3 7,366,946 ROM redundancy in ROM embedded DRAM
4 7,366,942 Method and apparatus for high-speed input sampling
5 7,366,920 System and method for selective memory module power management
6 7,366,864 Memory hub architecture having programmable lane widths
7 7,366,051 Word line driver circuitry and methods for using the same
8 7,366,045 Power circuits for reducing a number of power supply voltage taps required for sensing a resistive memory
9 7,366,041 Input buffer for low voltage operation
10 7,366,030 Simultaneous read circuit for multiple memory cells
11 7,366,027 Method and apparatus for erasing memory
12 7,366,021 Method and apparatus for sensing flash memory using delta sigma modulation
13 7,366,017 Method for modifying data more than once in a multi-level cell memory location within a memory array
14 7,366,013 Single level cell programming in a multiple level cell non-volatile memory device
15 7,366,003 Method of operating a complementary bit resistance memory sensor and method of operation
16 7,365,784 Column sample-and-hold cell for CMOS APS sensor
17 7,365,773 CMOS APS with stacked avalanche multiplication layer and low voltage readout electronics
18 7,365,597 Switched capacitor amplifier with higher gain and improved closed-loop gain accuracy
19 7,365,570 Pseudo-differential output driver with high immunity to noise and jitter
20 7,365,558 In-tray burn-in board, device and test assembly for testing integrated circuit devices in situ on processing trays
21 7,365,424 Microelectronic component assemblies with recessed wire bonds and methods of making same
22 7,365,420 Semiconductor packages and methods for making and using same
23 7,365,411 Resistance variable memory with temperature tolerant materials
24 7,365,409 Two-transistor pixel with buried reset channel and method of formation
25 7,365,388 Embedded trap direct tunnel non-volatile memory
26 7,365,385 DRAM layout with vertical FETs and method of formation
27 7,365,384 Trench buried bit line memory devices and methods thereof
28 7,365,305 Layered lens structures and methods of production in which radius of curvature of the upper lens can be varied
29 7,365,028 Methods of forming metal oxide and semimetal oxide
30 7,365,027 ALD of amorphous lanthanide doped TiO.sub.x films
31 7,364,997 Methods of forming integrated circuitry and methods of forming local interconnects
32 7,364,985 Method for creating electrical pathways for semiconductor device structures using laser machining processes
33 7,364,981 Methods of forming trench isolation in the fabrication of integrated circuitry, methods of fabricating memory circuitry, integrated circuitry and memory integrated circuitry
34 7,364,966 Method for forming a buried digit line with self aligning spacing layer and contact plugs during the formation of a semiconductor device, semiconductor devices, and systems including same
35 7,364,934 Microelectronic imaging units and methods of manufacturing microelectronic imaging units
36 7,364,644 Silver selenide film stoichiometry and morphology control in sputter deposition
37 7,363,694 Method of testing using compliant contact structures, contactor cards and test system